In my design I need to use the following design approach：

But after generating HDL code using HDLCoder, the report suggests that:
"Adaptive pipelining is not supported if the block is in a feedback loop. Number of registers required: 2; Number of registers inserted: 0.（from MATLABr21b）” and "Unable to insert required number of pipeline registers because the block, gain, is in a feedback loop and there are not enough latency budget at the output of the block. Number of registers required: 2; number of registers inserted: 0. Consider increasing the latency budget by adding more design delays in the feedback loop or using clock-rate pipelining.(from MATLABr23b）"
At the moment I don’t know how to go about modifying it, I’d like to know if it’s feasible for me to do so, and also how this needs to be implemented for the clock rate pipeline, I don’t have the slightest clue, and I didn’t understand what I should do from reading the official instructions. I hope to get the guidance of professionals, thank you very much.
If you need to provide more instructions, I am very happy to add!
Here is a screenshot of the reportIn my design I need to use the following design approach：

But after generating HDL code using HDLCoder, the report suggests that:
"Adaptive pipelining is not supported if the block is in a feedback loop. Number of registers required: 2; Number of registers inserted: 0.（from MATLABr21b）” and "Unable to insert required number of pipeline registers because the block, gain, is in a feedback loop and there are not enough latency budget at the output of the block. Number of registers required: 2; number of registers inserted: 0. Consider increasing the latency budget by adding more design delays in the feedback loop or using clock-rate pipelining.(from MATLABr23b）"
At the moment I don’t know how to go about modifying it, I’d like to know if it’s feasible for me to do so, and also how this needs to be implemented for the clock rate pipeline, I don’t have the slightest clue, and I didn’t understand what I should do from reading the official instructions. I hope to get the guidance of professionals, thank you very much.
If you need to provide more instructions, I am very happy to add!
Here is a screenshot of the report In my design I need to use the following design approach：

But after generating HDL code using HDLCoder, the report suggests that:
"Adaptive pipelining is not supported if the block is in a feedback loop. Number of registers required: 2; Number of registers inserted: 0.（from MATLABr21b）” and "Unable to insert required number of pipeline registers because the block, gain, is in a feedback loop and there are not enough latency budget at the output of the block. Number of registers required: 2; number of registers inserted: 0. Consider increasing the latency budget by adding more design delays in the feedback loop or using clock-rate pipelining.(from MATLABr23b）"
At the moment I don’t know how to go about modifying it, I’d like to know if it’s feasible for me to do so, and also how this needs to be implemented for the clock rate pipeline, I don’t have the slightest clue, and I didn’t understand what I should do from reading the official instructions. I hope to get the guidance of professionals, thank you very much.
If you need to provide more instructions, I am very happy to add!
Here is a screenshot of the report adaptive pipelining design, registers MATLAB Answers — New Questions

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