Dear all,

I am using SoC Blockset for a simple design for AMD Zynq Ultrascale+ ZCU111 evaluation board.

If I understand it correctly, the SoC Blockset add-on uses HDL coder to generate code for FPGA part of the SoC, but this is done through the SoC Builder interface, in which there are much less flexibility then in HDL coder. Does SoC Builder do some FPGA resource optimizations for build? How can I see the resource mapping? Can I change the mapping manually (for a better optimization, e.g.) or is it not possible to make a better mapping then the one produced automatically?

Thank you for your answers!Dear all,

I am using SoC Blockset for a simple design for AMD Zynq Ultrascale+ ZCU111 evaluation board.

If I understand it correctly, the SoC Blockset add-on uses HDL coder to generate code for FPGA part of the SoC, but this is done through the SoC Builder interface, in which there are much less flexibility then in HDL coder. Does SoC Builder do some FPGA resource optimizations for build? How can I see the resource mapping? Can I change the mapping manually (for a better optimization, e.g.) or is it not possible to make a better mapping then the one produced automatically?

Thank you for your answers! Dear all,

I am using SoC Blockset for a simple design for AMD Zynq Ultrascale+ ZCU111 evaluation board.

If I understand it correctly, the SoC Blockset add-on uses HDL coder to generate code for FPGA part of the SoC, but this is done through the SoC Builder interface, in which there are much less flexibility then in HDL coder. Does SoC Builder do some FPGA resource optimizations for build? How can I see the resource mapping? Can I change the mapping manually (for a better optimization, e.g.) or is it not possible to make a better mapping then the one produced automatically?

Thank you for your answers! hdl coder, soc builder, soc blockset, mapping, fpga, programmable logic, optimization MATLAB Answers — New Questions

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