Dear all,

I am using SoC Blockset for a simple receiver design for AMD Zynq Ultrascale+ ZCU111 evaluation board.
The Top model consists of the following parts: Signal generation subsystem (part of a testbench) -> RF data converter block -> FPGA referenced model -> AXI4-Stream to Sofrtare block (PS memory is selected) -> Processor subsystem (with Task Manager block and Processor referenced model inside) -> Subsystem with logic to view the output of the design from the Processor side (part of the testbench).
Now I want to deploy the design: using SoC Blockset I generate a bitstream and open an external mode model for the processor.
The question is: At which step of the deployment are the settings of RFDC and AXI4-Stream to Software blocks are applied to HW? First, the bitstream for FPGA model is generated and loaded, FPGA starts running, are the DACs/ADCs and PS memory already configured and working by that point? Or do they start as soon as code for the external mode model is generated and the processes are run on the target Processor?

This is important because if I, for example, I want to deploy the processor application and FPGA degisn separately at different time, bypassing SoC Bulder workflow, I need to know how to configure data converters and memory manually.

Thank you!Dear all,

I am using SoC Blockset for a simple receiver design for AMD Zynq Ultrascale+ ZCU111 evaluation board.
The Top model consists of the following parts: Signal generation subsystem (part of a testbench) -> RF data converter block -> FPGA referenced model -> AXI4-Stream to Sofrtare block (PS memory is selected) -> Processor subsystem (with Task Manager block and Processor referenced model inside) -> Subsystem with logic to view the output of the design from the Processor side (part of the testbench).
Now I want to deploy the design: using SoC Blockset I generate a bitstream and open an external mode model for the processor.
The question is: At which step of the deployment are the settings of RFDC and AXI4-Stream to Software blocks are applied to HW? First, the bitstream for FPGA model is generated and loaded, FPGA starts running, are the DACs/ADCs and PS memory already configured and working by that point? Or do they start as soon as code for the external mode model is generated and the processes are run on the target Processor?

This is important because if I, for example, I want to deploy the processor application and FPGA degisn separately at different time, bypassing SoC Bulder workflow, I need to know how to configure data converters and memory manually.

Thank you! Dear all,

I am using SoC Blockset for a simple receiver design for AMD Zynq Ultrascale+ ZCU111 evaluation board.
The Top model consists of the following parts: Signal generation subsystem (part of a testbench) -> RF data converter block -> FPGA referenced model -> AXI4-Stream to Sofrtare block (PS memory is selected) -> Processor subsystem (with Task Manager block and Processor referenced model inside) -> Subsystem with logic to view the output of the design from the Processor side (part of the testbench).
Now I want to deploy the design: using SoC Blockset I generate a bitstream and open an external mode model for the processor.
The question is: At which step of the deployment are the settings of RFDC and AXI4-Stream to Software blocks are applied to HW? First, the bitstream for FPGA model is generated and loaded, FPGA starts running, are the DACs/ADCs and PS memory already configured and working by that point? Or do they start as soon as code for the external mode model is generated and the processes are run on the target Processor?

This is important because if I, for example, I want to deploy the processor application and FPGA degisn separately at different time, bypassing SoC Bulder workflow, I need to know how to configure data converters and memory manually.

Thank you! rfdc, code generation, embedded coder, soc builder, fpga, target device, soc, zcu111 MATLAB Answers — New Questions

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