How to generate Generic VHDL from simulink for sysgen model?
I have used xilinx basic blocks to design a model. I wanted to generate generic VHDL without xilinx specific references. Eventhough i have choosen Behavioural HDL for implementation generated vhdl consist of xilinx specific DFlip-Flop and SRLUTs. Kindly let me know if there is a way? if the option is not being applied then how can we write a matlab sript to set automatically without doing it manually?I have used xilinx basic blocks to design a model. I wanted to generate generic VHDL without xilinx specific references. Eventhough i have choosen Behavioural HDL for implementation generated vhdl consist of xilinx specific DFlip-Flop and SRLUTs. Kindly let me know if there is a way? if the option is not being applied then how can we write a matlab sript to set automatically without doing it manually? I have used xilinx basic blocks to design a model. I wanted to generate generic VHDL without xilinx specific references. Eventhough i have choosen Behavioural HDL for implementation generated vhdl consist of xilinx specific DFlip-Flop and SRLUTs. Kindly let me know if there is a way? if the option is not being applied then how can we write a matlab sript to set automatically without doing it manually? systemgenerator, vhdl, matlab, xilinx, simulink MATLAB Answers — New Questions