I’m trying to understand the impact of a clock jitter in an embedded system and its effect on an FFT calculation.
Thus, I’m creating a jittered clock in Simulink, which triggers a sample & hold subsystem, which shall create discrete samples (like in an ADC) of a continuous 20 Hz sine input signal.
Due to the jittered nature of the clock, I can’t use a fixed sample rate (or would need to choose a way higher sample rate to model the jitter), thus I chose the auto solver and continuous sample rates.

Sample rate legend:

I tried to follow Model Effect of Temperature and Jitter on Crystal Oscillation Frequency and created two options for the clock generation, hit scheduler and the variable pulse generator, but those seem not to make any difference.
In the model, you can choose to enable or disable the jitter. f0 is the nominal clock frequency, which is 1 kHz in this example.
There’s also a counter to visualize the number of clock cycles. Assuming a simulation time of 2.048 s, exactly 2048 clock cycles are generated, assuming no jitter, which makes sense given the 1 kHz clock. On my PC, when I enable the jitter, only 1822 clock cycles are present.
Below you can see the input signal (20 Hz sine), the clock, and the sampled signal:

In the detail view you can see the desired unsteady clock and the sampled signal.

While this looks good at the first glance, I was wondering, how many data points per step are really generated? Can the be answered given that SL chooses the variable sample rate? Is there a way to generate exactly one data point/sample per clock trigger?
If the clock was stable, I’d use a rate transition (which is in the model, see the screenshot). But rate transitions can’t have variable sample rates, e.g. via an in-port it seems.
My next steps would be to calculate the FFT on those samples. But I’m not sure how to make sure that there’s one sample per clock.
In the model you can see various approaches I’ve tried to use to calculate the FFT, but I’m not sure if any is correct.
Unfortunately, the Spectrum Analyzer as well as the buffer blocks need non-continuous sample rates, thus the rate transition seems to be the only choice? But that implies a constant sample rate, which is not true…
Another trial was to calculate the FFT in a MATLAB function but not sure if that approach is correct.
Ultimately I want to estimate the error of the frequency bin estimation in the FFT given an unstable clock. I.e., when there’s no jitter in the clock, the 20 Hz sine should appear perfectly. But what if there’s a jitter?
Can the Spectrum Analyzer block used without discrete sample rates?
Are there any concepts I could use I’m not aware of? Right now I’m using normal rising edge triggers, would function-call triggers change something? Again, I’d like to make sure that there’s exactly one data point/sample available per clock edge – just like it would be in the embedded device’s ADC interrupt.

Is the problem clear? You need any more information?

Thanks for any input,
Jan

The model is attached for your reference.I’m trying to understand the impact of a clock jitter in an embedded system and its effect on an FFT calculation.
Thus, I’m creating a jittered clock in Simulink, which triggers a sample & hold subsystem, which shall create discrete samples (like in an ADC) of a continuous 20 Hz sine input signal.
Due to the jittered nature of the clock, I can’t use a fixed sample rate (or would need to choose a way higher sample rate to model the jitter), thus I chose the auto solver and continuous sample rates.

Sample rate legend:

I tried to follow Model Effect of Temperature and Jitter on Crystal Oscillation Frequency and created two options for the clock generation, hit scheduler and the variable pulse generator, but those seem not to make any difference.
In the model, you can choose to enable or disable the jitter. f0 is the nominal clock frequency, which is 1 kHz in this example.
There’s also a counter to visualize the number of clock cycles. Assuming a simulation time of 2.048 s, exactly 2048 clock cycles are generated, assuming no jitter, which makes sense given the 1 kHz clock. On my PC, when I enable the jitter, only 1822 clock cycles are present.
Below you can see the input signal (20 Hz sine), the clock, and the sampled signal:

In the detail view you can see the desired unsteady clock and the sampled signal.

While this looks good at the first glance, I was wondering, how many data points per step are really generated? Can the be answered given that SL chooses the variable sample rate? Is there a way to generate exactly one data point/sample per clock trigger?
If the clock was stable, I’d use a rate transition (which is in the model, see the screenshot). But rate transitions can’t have variable sample rates, e.g. via an in-port it seems.
My next steps would be to calculate the FFT on those samples. But I’m not sure how to make sure that there’s one sample per clock.
In the model you can see various approaches I’ve tried to use to calculate the FFT, but I’m not sure if any is correct.
Unfortunately, the Spectrum Analyzer as well as the buffer blocks need non-continuous sample rates, thus the rate transition seems to be the only choice? But that implies a constant sample rate, which is not true…
Another trial was to calculate the FFT in a MATLAB function but not sure if that approach is correct.
Ultimately I want to estimate the error of the frequency bin estimation in the FFT given an unstable clock. I.e., when there’s no jitter in the clock, the 20 Hz sine should appear perfectly. But what if there’s a jitter?
Can the Spectrum Analyzer block used without discrete sample rates?
Are there any concepts I could use I’m not aware of? Right now I’m using normal rising edge triggers, would function-call triggers change something? Again, I’d like to make sure that there’s exactly one data point/sample available per clock edge – just like it would be in the embedded device’s ADC interrupt.

Is the problem clear? You need any more information?

Thanks for any input,
Jan

The model is attached for your reference. I’m trying to understand the impact of a clock jitter in an embedded system and its effect on an FFT calculation.
Thus, I’m creating a jittered clock in Simulink, which triggers a sample & hold subsystem, which shall create discrete samples (like in an ADC) of a continuous 20 Hz sine input signal.
Due to the jittered nature of the clock, I can’t use a fixed sample rate (or would need to choose a way higher sample rate to model the jitter), thus I chose the auto solver and continuous sample rates.

Sample rate legend:

I tried to follow Model Effect of Temperature and Jitter on Crystal Oscillation Frequency and created two options for the clock generation, hit scheduler and the variable pulse generator, but those seem not to make any difference.
In the model, you can choose to enable or disable the jitter. f0 is the nominal clock frequency, which is 1 kHz in this example.
There’s also a counter to visualize the number of clock cycles. Assuming a simulation time of 2.048 s, exactly 2048 clock cycles are generated, assuming no jitter, which makes sense given the 1 kHz clock. On my PC, when I enable the jitter, only 1822 clock cycles are present.
Below you can see the input signal (20 Hz sine), the clock, and the sampled signal:

In the detail view you can see the desired unsteady clock and the sampled signal.

While this looks good at the first glance, I was wondering, how many data points per step are really generated? Can the be answered given that SL chooses the variable sample rate? Is there a way to generate exactly one data point/sample per clock trigger?
If the clock was stable, I’d use a rate transition (which is in the model, see the screenshot). But rate transitions can’t have variable sample rates, e.g. via an in-port it seems.
My next steps would be to calculate the FFT on those samples. But I’m not sure how to make sure that there’s one sample per clock.
In the model you can see various approaches I’ve tried to use to calculate the FFT, but I’m not sure if any is correct.
Unfortunately, the Spectrum Analyzer as well as the buffer blocks need non-continuous sample rates, thus the rate transition seems to be the only choice? But that implies a constant sample rate, which is not true…
Another trial was to calculate the FFT in a MATLAB function but not sure if that approach is correct.
Ultimately I want to estimate the error of the frequency bin estimation in the FFT given an unstable clock. I.e., when there’s no jitter in the clock, the 20 Hz sine should appear perfectly. But what if there’s a jitter?
Can the Spectrum Analyzer block used without discrete sample rates?
Are there any concepts I could use I’m not aware of? Right now I’m using normal rising edge triggers, would function-call triggers change something? Again, I’d like to make sure that there’s exactly one data point/sample available per clock edge – just like it would be in the embedded device’s ADC interrupt.

Is the problem clear? You need any more information?

Thanks for any input,
Jan

The model is attached for your reference. simulink, clock jitter, fft, sampling, rate transition MATLAB Answers — New Questions

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