I am using SoC Blockset to create a model to run on the Xilinx Zynq Ultrascale+ ZCU216 RFSoC board. I have simulated and run this example on the board, so I know that the DACs and ADCs works: Transmit and Receive Tone Using Xilinx RFSoC Device – Part 2 Deployment – MATLAB & Simulink (mathworks.com)
I created a new Simulink model using the RFSoC template under SoC Blockset. I added my logic (generating a tone on the DAC and reading it on the ADC) and was able to simulate successfully. I am able to also build successfully in external mode, but when I load the bitstream, I do not see any output on my scope. The counter does not go up and no output shows up. Does anyone know what is wrong?I am using SoC Blockset to create a model to run on the Xilinx Zynq Ultrascale+ ZCU216 RFSoC board. I have simulated and run this example on the board, so I know that the DACs and ADCs works: Transmit and Receive Tone Using Xilinx RFSoC Device – Part 2 Deployment – MATLAB & Simulink (mathworks.com)
I created a new Simulink model using the RFSoC template under SoC Blockset. I added my logic (generating a tone on the DAC and reading it on the ADC) and was able to simulate successfully. I am able to also build successfully in external mode, but when I load the bitstream, I do not see any output on my scope. The counter does not go up and no output shows up. Does anyone know what is wrong? I am using SoC Blockset to create a model to run on the Xilinx Zynq Ultrascale+ ZCU216 RFSoC board. I have simulated and run this example on the board, so I know that the DACs and ADCs works: Transmit and Receive Tone Using Xilinx RFSoC Device – Part 2 Deployment – MATLAB & Simulink (mathworks.com)
I created a new Simulink model using the RFSoC template under SoC Blockset. I added my logic (generating a tone on the DAC and reading it on the ADC) and was able to simulate successfully. I am able to also build successfully in external mode, but when I load the bitstream, I do not see any output on my scope. The counter does not go up and no output shows up. Does anyone know what is wrong? xilinx, zynq, simulink, soc blockset MATLAB Answers — New Questions

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