I have an application where i’m generating HDL in a cyclone V for an MII interface to an Ethernet PHY. I read the documentation about using a triggered subystem as a separate clock ( https://www.mathworks.com/help/hdlcoder/ug/use-triggered-subsystem-for-asynchronous-clock-domain.html ) and I noticed the verilog code does treat the RXC signal as a true clock. However, I’m having trouble getting the CDC logic to convert properly. It seems even when I use a Dual Rate Dual Port RAM with different sample rates, it still uses a single clock with clock enables to derive the different rates rather than using RXC as the clock for port A and IPCORE_CLK for port B. I also see no option to use an asynchronous FIFO (dcfifo) in the libraray browser. How can i properly implement CDC logic using simulink tools?I have an application where i’m generating HDL in a cyclone V for an MII interface to an Ethernet PHY. I read the documentation about using a triggered subystem as a separate clock ( https://www.mathworks.com/help/hdlcoder/ug/use-triggered-subsystem-for-asynchronous-clock-domain.html ) and I noticed the verilog code does treat the RXC signal as a true clock. However, I’m having trouble getting the CDC logic to convert properly. It seems even when I use a Dual Rate Dual Port RAM with different sample rates, it still uses a single clock with clock enables to derive the different rates rather than using RXC as the clock for port A and IPCORE_CLK for port B. I also see no option to use an asynchronous FIFO (dcfifo) in the libraray browser. How can i properly implement CDC logic using simulink tools? I have an application where i’m generating HDL in a cyclone V for an MII interface to an Ethernet PHY. I read the documentation about using a triggered subystem as a separate clock ( https://www.mathworks.com/help/hdlcoder/ug/use-triggered-subsystem-for-asynchronous-clock-domain.html ) and I noticed the verilog code does treat the RXC signal as a true clock. However, I’m having trouble getting the CDC logic to convert properly. It seems even when I use a Dual Rate Dual Port RAM with different sample rates, it still uses a single clock with clock enables to derive the different rates rather than using RXC as the clock for port A and IPCORE_CLK for port B. I also see no option to use an asynchronous FIFO (dcfifo) in the libraray browser. How can i properly implement CDC logic using simulink tools? hdl coder MATLAB Answers — New Questions
