I’m having trouble understanding this error from HDL coder:
Failed All the DUT ports connecting to the "f2h_sdram0 Read" interface must be running at the fastest rate in the generated DUT HDL code. Port "data_in" uses sample rate of 5e-06, the fastest rate in the DUT HDL code is 2e-07.

Error using hdlturnkey.data.Channel/validateCodeGenPortRate
All the DUT ports connecting to the "f2h_sdram0 Read" interface must be running at the fastest rate in the generated DUT HDL code. Port
"data_in" uses sample rate of 5e-06, the fastest rate in the DUT HDL code is 2e-07.

I want to read from a particular address in memory every 5 us. I don’t want to read every 2e-7 seconds and flood the bus with uneeded read requests. I tried checking the timing legend and nothing even seems to be running at 2e-07 so i’m not sure where it is getting that rate from in the first place.
Am i approaching the sampling logic for this incorrectly? Instead of controlling when it performs a read by changing the execution time of the read-slave-to-master interface and Data signals, should i let the execution time be set to -1 (inherited) and control the read time by changing the rd_dvalid signal using temporal logic in my stateflow chart? Thanks for any help.I’m having trouble understanding this error from HDL coder:
Failed All the DUT ports connecting to the "f2h_sdram0 Read" interface must be running at the fastest rate in the generated DUT HDL code. Port "data_in" uses sample rate of 5e-06, the fastest rate in the DUT HDL code is 2e-07.

Error using hdlturnkey.data.Channel/validateCodeGenPortRate
All the DUT ports connecting to the "f2h_sdram0 Read" interface must be running at the fastest rate in the generated DUT HDL code. Port
"data_in" uses sample rate of 5e-06, the fastest rate in the DUT HDL code is 2e-07.

I want to read from a particular address in memory every 5 us. I don’t want to read every 2e-7 seconds and flood the bus with uneeded read requests. I tried checking the timing legend and nothing even seems to be running at 2e-07 so i’m not sure where it is getting that rate from in the first place.
Am i approaching the sampling logic for this incorrectly? Instead of controlling when it performs a read by changing the execution time of the read-slave-to-master interface and Data signals, should i let the execution time be set to -1 (inherited) and control the read time by changing the rd_dvalid signal using temporal logic in my stateflow chart? Thanks for any help. I’m having trouble understanding this error from HDL coder:
Failed All the DUT ports connecting to the "f2h_sdram0 Read" interface must be running at the fastest rate in the generated DUT HDL code. Port "data_in" uses sample rate of 5e-06, the fastest rate in the DUT HDL code is 2e-07.

Error using hdlturnkey.data.Channel/validateCodeGenPortRate
All the DUT ports connecting to the "f2h_sdram0 Read" interface must be running at the fastest rate in the generated DUT HDL code. Port
"data_in" uses sample rate of 5e-06, the fastest rate in the DUT HDL code is 2e-07.

I want to read from a particular address in memory every 5 us. I don’t want to read every 2e-7 seconds and flood the bus with uneeded read requests. I tried checking the timing legend and nothing even seems to be running at 2e-07 so i’m not sure where it is getting that rate from in the first place.
Am i approaching the sampling logic for this incorrectly? Instead of controlling when it performs a read by changing the execution time of the read-slave-to-master interface and Data signals, should i let the execution time be set to -1 (inherited) and control the read time by changing the rd_dvalid signal using temporal logic in my stateflow chart? Thanks for any help. hdl coder MATLAB Answers — New Questions

​