HI,
I try to design True Dual Port RAM on Ultra RAM. I use block primitive True Dual Port RAM in 2024a and set RAMDirective ‘ultra’. Generated code has this attribute. But when implemen step in Vivado, i have info, that attribute ultra is ignored because invalid write mode. And after implementing my RAM design by block RAM, but i need based on Ultra RAM
Please, give advice about this problemHI,
I try to design True Dual Port RAM on Ultra RAM. I use block primitive True Dual Port RAM in 2024a and set RAMDirective ‘ultra’. Generated code has this attribute. But when implemen step in Vivado, i have info, that attribute ultra is ignored because invalid write mode. And after implementing my RAM design by block RAM, but i need based on Ultra RAM
Please, give advice about this problem HI,
I try to design True Dual Port RAM on Ultra RAM. I use block primitive True Dual Port RAM in 2024a and set RAMDirective ‘ultra’. Generated code has this attribute. But when implemen step in Vivado, i have info, that attribute ultra is ignored because invalid write mode. And after implementing my RAM design by block RAM, but i need based on Ultra RAM
Please, give advice about this problem hdl coder, ultra ram, ramdirective, simulink MATLAB Answers — New Questions

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