SoC Builder stucked on “Synthesize design”
Hello. I’m attempting to deploy the "RFSoC Template" from the SoC Blockset, which involves a simple loopback from a DAC to an ADC channel for the ZCU-111 board. I can open and simulate the top-level model successfully. However, when I try to use the "SoC Builder" via the "Configure, Build & Deploy" button, the wizard becomes indefinitely stuck at the "Synthesize design" step. All preceding steps execute without errors. The last few lines in the MATLAB command window indicate an "Error while evaluating TimerFcn for timer ‘BuildStatusTimer_soc_rfsoc_top’ as follows:
### Workflow complete.
———- Generating Xilinx Design Tcl File ———-
———- Generating constraints file ———-
———- Creating Vivado project ———-
———- Building Vivado project with 6 parallel jobs ———-
### Using the SoC system information from ‘/home/canisio/Workspace/Simulink_RFSoC/soc_prj/socsysinfo.mat’
Error while evaluating TimerFcn for timer ‘BuildStatusTimer_soc_rfsoc_top’
Could not open file /home/canisio/Workspace/Simulink_RFSoC/soc_prj/vivado_build_prj.log. No such file or directory.
Even though the GUI indicates "Project build successfully started in a separate window," no additional window or prompt appears, aside from the "code generation report." I opened the Linux "System Monitor," and judging by the core usage, there’s definitely no synthesis occurring.
I’m utilizing Matlab/Simulink 2024a alongside Vivado tools 2023.1 on Ubuntu 22.04.4 LTS. Vivado has the necessary licenses for the RFSoC board and functions correctly; I’ve successfully opened the created project and generated the respective bitstream. However, this deviates from the anticipated workflow for the SoC Blockset, and I aim to utilize the complete MathWorks framework.
The SD card to boot the board was configured according to the instructions provided in the installation of the "SoC Blockset Support Package for Xilinx Devices" version 24.1.1. I’m able to connect via JTAG and ping to and from the board.
Am I overlooking any additional configurations? Thank you in advance.Hello. I’m attempting to deploy the "RFSoC Template" from the SoC Blockset, which involves a simple loopback from a DAC to an ADC channel for the ZCU-111 board. I can open and simulate the top-level model successfully. However, when I try to use the "SoC Builder" via the "Configure, Build & Deploy" button, the wizard becomes indefinitely stuck at the "Synthesize design" step. All preceding steps execute without errors. The last few lines in the MATLAB command window indicate an "Error while evaluating TimerFcn for timer ‘BuildStatusTimer_soc_rfsoc_top’ as follows:
### Workflow complete.
———- Generating Xilinx Design Tcl File ———-
———- Generating constraints file ———-
———- Creating Vivado project ———-
———- Building Vivado project with 6 parallel jobs ———-
### Using the SoC system information from ‘/home/canisio/Workspace/Simulink_RFSoC/soc_prj/socsysinfo.mat’
Error while evaluating TimerFcn for timer ‘BuildStatusTimer_soc_rfsoc_top’
Could not open file /home/canisio/Workspace/Simulink_RFSoC/soc_prj/vivado_build_prj.log. No such file or directory.
Even though the GUI indicates "Project build successfully started in a separate window," no additional window or prompt appears, aside from the "code generation report." I opened the Linux "System Monitor," and judging by the core usage, there’s definitely no synthesis occurring.
I’m utilizing Matlab/Simulink 2024a alongside Vivado tools 2023.1 on Ubuntu 22.04.4 LTS. Vivado has the necessary licenses for the RFSoC board and functions correctly; I’ve successfully opened the created project and generated the respective bitstream. However, this deviates from the anticipated workflow for the SoC Blockset, and I aim to utilize the complete MathWorks framework.
The SD card to boot the board was configured according to the instructions provided in the installation of the "SoC Blockset Support Package for Xilinx Devices" version 24.1.1. I’m able to connect via JTAG and ping to and from the board.
Am I overlooking any additional configurations? Thank you in advance. Hello. I’m attempting to deploy the "RFSoC Template" from the SoC Blockset, which involves a simple loopback from a DAC to an ADC channel for the ZCU-111 board. I can open and simulate the top-level model successfully. However, when I try to use the "SoC Builder" via the "Configure, Build & Deploy" button, the wizard becomes indefinitely stuck at the "Synthesize design" step. All preceding steps execute without errors. The last few lines in the MATLAB command window indicate an "Error while evaluating TimerFcn for timer ‘BuildStatusTimer_soc_rfsoc_top’ as follows:
### Workflow complete.
———- Generating Xilinx Design Tcl File ———-
———- Generating constraints file ———-
———- Creating Vivado project ———-
———- Building Vivado project with 6 parallel jobs ———-
### Using the SoC system information from ‘/home/canisio/Workspace/Simulink_RFSoC/soc_prj/socsysinfo.mat’
Error while evaluating TimerFcn for timer ‘BuildStatusTimer_soc_rfsoc_top’
Could not open file /home/canisio/Workspace/Simulink_RFSoC/soc_prj/vivado_build_prj.log. No such file or directory.
Even though the GUI indicates "Project build successfully started in a separate window," no additional window or prompt appears, aside from the "code generation report." I opened the Linux "System Monitor," and judging by the core usage, there’s definitely no synthesis occurring.
I’m utilizing Matlab/Simulink 2024a alongside Vivado tools 2023.1 on Ubuntu 22.04.4 LTS. Vivado has the necessary licenses for the RFSoC board and functions correctly; I’ve successfully opened the created project and generated the respective bitstream. However, this deviates from the anticipated workflow for the SoC Blockset, and I aim to utilize the complete MathWorks framework.
The SD card to boot the board was configured according to the instructions provided in the installation of the "SoC Blockset Support Package for Xilinx Devices" version 24.1.1. I’m able to connect via JTAG and ping to and from the board.
Am I overlooking any additional configurations? Thank you in advance. soc, xilinx, zcu, rfsoc, soc builder, synthesis, stuck MATLAB Answers — New Questions