How to get Simulink HDL Coder RAM with non power of 2 depth.
Simulink RAMs ask the user for the address bits instead of the data depth, and then generate HDL using a power-of-2 depth. This may result in extra, unused RAMs to be inferred by a synthesis tool. For example if your RAM could be implemented in 3 chained Block RAMs of depth 2^10 for a total depth of 3*2^10 but due to the Simulink RAM specifying a depth of 2^12 (based on needing 12 address bits) the tool will use 4 Block RAMs instead of the minimum 3.
Is it possible to get Simulink to generate RAM HDL with a specified depth? The output code would look something like below:
module SimpleDualPortRAM_generic
(clk,
wr_din,
wr_addr,
wr_en,
rd_addr,
dout);
parameter integer DataWidth = 9;
parameter integer DataDepth = 12288;
localparam AddrWidth = $clog2(DataDepth);
input clk;
input [DataWidth – 1:0] wr_din; // parameterized width
input [AddrWidth – 1:0] wr_addr; // parameterized width
input wr_en; // ufix1
input [AddrWidth – 1:0] rd_addr; // parameterized width
output [DataWidth – 1:0] dout; // parameterized width
reg [DataWidth – 1:0] ram [DataDepth – 1:0];
reg [DataWidth – 1:0] data_int;
always @(posedge clk)
begin : SimpleDualPortRAM_generic_process
if (wr_en == 1’b1) begin
ram[wr_addr] <= wr_din;
end
data_int <= ram[rd_addr];
end
assign dout = data_int;
endmodule // SimpleDualPortRAM_genericSimulink RAMs ask the user for the address bits instead of the data depth, and then generate HDL using a power-of-2 depth. This may result in extra, unused RAMs to be inferred by a synthesis tool. For example if your RAM could be implemented in 3 chained Block RAMs of depth 2^10 for a total depth of 3*2^10 but due to the Simulink RAM specifying a depth of 2^12 (based on needing 12 address bits) the tool will use 4 Block RAMs instead of the minimum 3.
Is it possible to get Simulink to generate RAM HDL with a specified depth? The output code would look something like below:
module SimpleDualPortRAM_generic
(clk,
wr_din,
wr_addr,
wr_en,
rd_addr,
dout);
parameter integer DataWidth = 9;
parameter integer DataDepth = 12288;
localparam AddrWidth = $clog2(DataDepth);
input clk;
input [DataWidth – 1:0] wr_din; // parameterized width
input [AddrWidth – 1:0] wr_addr; // parameterized width
input wr_en; // ufix1
input [AddrWidth – 1:0] rd_addr; // parameterized width
output [DataWidth – 1:0] dout; // parameterized width
reg [DataWidth – 1:0] ram [DataDepth – 1:0];
reg [DataWidth – 1:0] data_int;
always @(posedge clk)
begin : SimpleDualPortRAM_generic_process
if (wr_en == 1’b1) begin
ram[wr_addr] <= wr_din;
end
data_int <= ram[rd_addr];
end
assign dout = data_int;
endmodule // SimpleDualPortRAM_generic Simulink RAMs ask the user for the address bits instead of the data depth, and then generate HDL using a power-of-2 depth. This may result in extra, unused RAMs to be inferred by a synthesis tool. For example if your RAM could be implemented in 3 chained Block RAMs of depth 2^10 for a total depth of 3*2^10 but due to the Simulink RAM specifying a depth of 2^12 (based on needing 12 address bits) the tool will use 4 Block RAMs instead of the minimum 3.
Is it possible to get Simulink to generate RAM HDL with a specified depth? The output code would look something like below:
module SimpleDualPortRAM_generic
(clk,
wr_din,
wr_addr,
wr_en,
rd_addr,
dout);
parameter integer DataWidth = 9;
parameter integer DataDepth = 12288;
localparam AddrWidth = $clog2(DataDepth);
input clk;
input [DataWidth – 1:0] wr_din; // parameterized width
input [AddrWidth – 1:0] wr_addr; // parameterized width
input wr_en; // ufix1
input [AddrWidth – 1:0] rd_addr; // parameterized width
output [DataWidth – 1:0] dout; // parameterized width
reg [DataWidth – 1:0] ram [DataDepth – 1:0];
reg [DataWidth – 1:0] data_int;
always @(posedge clk)
begin : SimpleDualPortRAM_generic_process
if (wr_en == 1’b1) begin
ram[wr_addr] <= wr_din;
end
data_int <= ram[rd_addr];
end
assign dout = data_int;
endmodule // SimpleDualPortRAM_generic simulink ram, ram depth, ram, dual port ram MATLAB Answers — New Questions
