Hello,

I use the rs decoder of hdl coder. the simulation in matlab simulink is correct…
but when I load this code in fpga board and capture data by using the ILA, Its not same…
I think that when generated code is converted to verilog, difference is occured??
possible waring list..
optimization option
timing closure
tool version

1. optimization option : I set correct clock, fpga board, distributed pipeline … and so on.
-> I dont know that my setting value is correct????
2. timing satisfy, fpga clock : 16Mhz
3. matlab ver : 23a, vivado ver : 20.2

please give me check point….

thank you your corporation
Je Heo.Hello,

I use the rs decoder of hdl coder. the simulation in matlab simulink is correct…
but when I load this code in fpga board and capture data by using the ILA, Its not same…
I think that when generated code is converted to verilog, difference is occured??
possible waring list..
optimization option
timing closure
tool version

1. optimization option : I set correct clock, fpga board, distributed pipeline … and so on.
-> I dont know that my setting value is correct????
2. timing satisfy, fpga clock : 16Mhz
3. matlab ver : 23a, vivado ver : 20.2

please give me check point….

thank you your corporation
Je Heo. Hello,

I use the rs decoder of hdl coder. the simulation in matlab simulink is correct…
but when I load this code in fpga board and capture data by using the ILA, Its not same…
I think that when generated code is converted to verilog, difference is occured??
possible waring list..
optimization option
timing closure
tool version

1. optimization option : I set correct clock, fpga board, distributed pipeline … and so on.
-> I dont know that my setting value is correct????
2. timing satisfy, fpga clock : 16Mhz
3. matlab ver : 23a, vivado ver : 20.2

please give me check point….

thank you your corporation
Je Heo. hdl coder, rs decoder, fpga, generated hdl code, ila MATLAB Answers — New Questions

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