AXI4-Stream to Software clock frequency does not match FPGA clock frequency
Dear all,
I am using SoC Blockset add-on and checking out the example "Transmit and Receive Tone Using RFSoC Device" (https://www.mathworks.com/help/soc/ug/transmit-and-receive-tone-using-RFSoC-device-simulate.html). The FPGA Clock frequency (SampleTime) is set to 128MHz, but the AXI4-Stream to Software clock is set to 200MHz. How are then all the samples written to memory if the memory clock is slower than the sample production frequency?
How does in general AXI4-Stream to Software block work? The following qustions are not answered in the documentation (https://www.mathworks.com/help/soc/ref/axi4streamtosoftware.html):
1) Does one buffer contatin multiple bursts? If yes, how many?
2) With what rate is burst written to buffer?
3) With what rate are samples saved in burst (to be written to buffer later)?
4) Are samples written to FIFO with the same rate as in the previous question?
Thank you!Dear all,
I am using SoC Blockset add-on and checking out the example "Transmit and Receive Tone Using RFSoC Device" (https://www.mathworks.com/help/soc/ug/transmit-and-receive-tone-using-RFSoC-device-simulate.html). The FPGA Clock frequency (SampleTime) is set to 128MHz, but the AXI4-Stream to Software clock is set to 200MHz. How are then all the samples written to memory if the memory clock is slower than the sample production frequency?
How does in general AXI4-Stream to Software block work? The following qustions are not answered in the documentation (https://www.mathworks.com/help/soc/ref/axi4streamtosoftware.html):
1) Does one buffer contatin multiple bursts? If yes, how many?
2) With what rate is burst written to buffer?
3) With what rate are samples saved in burst (to be written to buffer later)?
4) Are samples written to FIFO with the same rate as in the previous question?
Thank you! Dear all,
I am using SoC Blockset add-on and checking out the example "Transmit and Receive Tone Using RFSoC Device" (https://www.mathworks.com/help/soc/ug/transmit-and-receive-tone-using-RFSoC-device-simulate.html). The FPGA Clock frequency (SampleTime) is set to 128MHz, but the AXI4-Stream to Software clock is set to 200MHz. How are then all the samples written to memory if the memory clock is slower than the sample production frequency?
How does in general AXI4-Stream to Software block work? The following qustions are not answered in the documentation (https://www.mathworks.com/help/soc/ref/axi4streamtosoftware.html):
1) Does one buffer contatin multiple bursts? If yes, how many?
2) With what rate is burst written to buffer?
3) With what rate are samples saved in burst (to be written to buffer later)?
4) Are samples written to FIFO with the same rate as in the previous question?
Thank you! clock, soc blockset, axi4-stream to software, axi4, fpga, sampling, fifo, buffer, burst, clock frequency MATLAB Answers — New Questions
