Hello,
I have a question regarding the relationship between Simulink sample rate and HDL Coder target frequency.
Is it okay if the Simulink sample rate is equal to the target frequency specified in HDL Coder?
I’ve often heard that the hardware clock rate (target frequency) should generally be at least 2× the sample rate to ensure proper timing and pipelining. But in Simulink and HDL Coder, I’m unsure how strict this rule is.
Specifically:
If I set my Simulink sample rate to 120 MSPS and also specify 120 MHz as the HDL Coder target frequency, is this configuration valid?
Or should the target frequency always be greater than the sample rate, even in fully pipelined or parallel architectures?
I’d really appreciate any clarification on how these two values interact and whether matching them could lead to timing issues during synthesis or implementation.
Thanks in advance!Hello,
I have a question regarding the relationship between Simulink sample rate and HDL Coder target frequency.
Is it okay if the Simulink sample rate is equal to the target frequency specified in HDL Coder?
I’ve often heard that the hardware clock rate (target frequency) should generally be at least 2× the sample rate to ensure proper timing and pipelining. But in Simulink and HDL Coder, I’m unsure how strict this rule is.
Specifically:
If I set my Simulink sample rate to 120 MSPS and also specify 120 MHz as the HDL Coder target frequency, is this configuration valid?
Or should the target frequency always be greater than the sample rate, even in fully pipelined or parallel architectures?
I’d really appreciate any clarification on how these two values interact and whether matching them could lead to timing issues during synthesis or implementation.
Thanks in advance! Hello,
I have a question regarding the relationship between Simulink sample rate and HDL Coder target frequency.
Is it okay if the Simulink sample rate is equal to the target frequency specified in HDL Coder?
I’ve often heard that the hardware clock rate (target frequency) should generally be at least 2× the sample rate to ensure proper timing and pipelining. But in Simulink and HDL Coder, I’m unsure how strict this rule is.
Specifically:
If I set my Simulink sample rate to 120 MSPS and also specify 120 MHz as the HDL Coder target frequency, is this configuration valid?
Or should the target frequency always be greater than the sample rate, even in fully pipelined or parallel architectures?
I’d really appreciate any clarification on how these two values interact and whether matching them could lead to timing issues during synthesis or implementation.
Thanks in advance! simulink, sample rate, hdl coder, target frequency MATLAB Answers — New Questions

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