Deep Learning HDL Workflow “Data size mismatch” after deployment – Possible device tree / AXI DMA configuration issue (ZCU111)

Hello,

I am working with Deep Learning HDL Toolbox on a custom reference design
with the Xilinx ZCU111 RFSoC board. I am able to successfully compile the network,
but I am encountering a deployment error.

Setup: – Board: ZCU111 RFSoC – Interface: PS GEM Ethernet – Reference design:
Custom (based on AXI-Stream DDR Memory Access : 3-AXIM) – Tool versions:
Vivado 2024.1, MATLAB (Deep Learning HDL Toolbox)

Workflow: I compile and deploy the network using: 1. compile(hW) 2.
deploy(hW) 3. predict(…)

Problem: The FPGA is programmed successfully, and the system reboots
correctly: – SSH connection is restored – Ping works

However, during deployment/predict, I get the following error on MATLAB:

Connection to the bitstream is no longer valid caused by error: Data
size mismatch.

Observations: – Bitstream programming is completed successfully – Device
tree is loaded and system boots – The error happens after deployment,
during runtime communication with FPGA.

Device Tree Concern: I suspect that the issue may be related to my device
tree definitions, especially: – dlprocessor IP – AXI stream to
memory-mapped interface (AXIS2AXIM / AXI2SMM) – DMA nodes (MM2S / S2MM)

Possible causes: Incorrect child node definitions

Questions: 1. What are the common causes of “Data size mismatch” in Deep
Learning HDL deployments? 2. Can this error be caused by incorrect
device tree configuration ? 3. Are there specific DTB
requirements for dlprocessor, AXIS2AXIM, and DMA nodes? 4. How can I
verify MATLAB runtime correctly binds to DTB nodes?

Also is there any official or working example of devicetree_dlhdl.dtb for:
Deep Learning HDL Toolbox
AXI-Stream DDR Memory Access (3-AXIM) reference design
ZCU111 (or similar Zynq UltraScale+ platforms)
I am especially interested in correct definitions for:
dlprocessor
AXIS2AXIM / AXI2SMM
DMA nodes (MM2S / S2MM)
mathworks-specific properties (mwipcore, channels, etc.)
If anyone has a working DTB or can point to an example (documentation, repo, or generated output), it would be very helpful.
Thanks!Hello,

I am working with Deep Learning HDL Toolbox on a custom reference design
with the Xilinx ZCU111 RFSoC board. I am able to successfully compile the network,
but I am encountering a deployment error.

Workflow: I compile and deploy the network using: 1. compile(hW) 2.
deploy(hW) 3. predict(…)

Problem: The FPGA is programmed successfully, and the system reboots
correctly: – SSH connection is restored – Ping works

However, during deployment/predict, I get the following error on MATLAB:

Connection to the bitstream is no longer valid caused by error: Data
size mismatch.

Observations: – Bitstream programming is completed successfully – Device
tree is loaded and system boots – The error happens after deployment,
during runtime communication with FPGA.

Possible causes: Incorrect child node definitions

I am working with Deep Learning HDL Toolbox on a custom reference design
with the Xilinx ZCU111 RFSoC board. I am able to successfully compile the network,
but I am encountering a deployment error.

Workflow: I compile and deploy the network using: 1. compile(hW) 2.
deploy(hW) 3. predict(…)

Problem: The FPGA is programmed successfully, and the system reboots
correctly: – SSH connection is restored – Ping works

However, during deployment/predict, I get the following error on MATLAB:

Connection to the bitstream is no longer valid caused by error: Data
size mismatch.

Observations: – Bitstream programming is completed successfully – Device
tree is loaded and system boots – The error happens after deployment,
during runtime communication with FPGA.

Possible causes: Incorrect child node definitions

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