Hello,
I am planning to deploy a CNN on my FPGA DE0 Nano Board (Cyclone IV), which is a custom board not directly supported by MATLAB. I have made myself comfortable with HDL Coder in Simulink by working on FIL (FPGA-in-the-loop) workflow for video processing application and hence I am looking for a similar workflow using Simulink, HDL coder, etc.
Could you outline the exact steps to follow on how do I go about developing a simple model using Simulink (maybe start with SqueezeNet to begin with on Deep Network Designer), making it hardware compatible and the process to deploy it on my FPGA? The resources available online talk about IP core generation, etc, which are a bit confusing and overwhelming.

Thanks :)Hello,
I am planning to deploy a CNN on my FPGA DE0 Nano Board (Cyclone IV), which is a custom board not directly supported by MATLAB. I have made myself comfortable with HDL Coder in Simulink by working on FIL (FPGA-in-the-loop) workflow for video processing application and hence I am looking for a similar workflow using Simulink, HDL coder, etc.
Could you outline the exact steps to follow on how do I go about developing a simple model using Simulink (maybe start with SqueezeNet to begin with on Deep Network Designer), making it hardware compatible and the process to deploy it on my FPGA? The resources available online talk about IP core generation, etc, which are a bit confusing and overwhelming.

Thanks  Hello,
I am planning to deploy a CNN on my FPGA DE0 Nano Board (Cyclone IV), which is a custom board not directly supported by MATLAB. I have made myself comfortable with HDL Coder in Simulink by working on FIL (FPGA-in-the-loop) workflow for video processing application and hence I am looking for a similar workflow using Simulink, HDL coder, etc.
Could you outline the exact steps to follow on how do I go about developing a simple model using Simulink (maybe start with SqueezeNet to begin with on Deep Network Designer), making it hardware compatible and the process to deploy it on my FPGA? The resources available online talk about IP core generation, etc, which are a bit confusing and overwhelming.

Thanks  fpga, simulink, neural network, hdl, fpga in the loop MATLAB Answers — New Questions

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