I’m trying to convert a discrete integrator block to Verilog and I’m getting the following error. I’m new to FPGA and don’t yet understand the numerous settings very well, but I’d like to figure out what’s going on. I managed to set discrete time everywhere, but I haven’t figured out this error yet. Please tell me.I’m trying to convert a discrete integrator block to Verilog and I’m getting the following error. I’m new to FPGA and don’t yet understand the numerous settings very well, but I’d like to figure out what’s going on. I managed to set discrete time everywhere, but I haven’t figured out this error yet. Please tell me. I’m trying to convert a discrete integrator block to Verilog and I’m getting the following error. I’m new to FPGA and don’t yet understand the numerous settings very well, but I’d like to figure out what’s going on. I managed to set discrete time everywhere, but I haven’t figured out this error yet. Please tell me. hdl, verilog, fpga, hdl coder, simulink, numerical integration MATLAB Answers — New Questions

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