Do the “ADC/DAC Interface” reference designs support Vivado 2022.1 or later?
I am trying to follow the HDL Coder demo "DAC and ADC Loopback Data Capture" for my ZCU111 board using MATLAB R2023a (or later) and Xilinx Vivado 2022.1 (or later):
https://www.mathworks.com/help/hdlcoder/ug/hdl-dac-adc-loopback-data-capture.html
The demo uses the "Real ADC/DAC Interface" reference design, as specified in step 1.2 in the HDL Workflow Advisor.
However, I encounter errors similar to the following at step 4.1 in the HDL Workflow Advisor:
The following IPs are not found in the IP Catalog:
xilinx.com:ip:usp_rf_data_converter:2.4
ERROR: [BD 5-216] VLNV <xilinx.com:ip:usp_rf_data_converter:2.4> is not supported for the current part.
The latest supported version for this part is: <2.5>
Based on the following MATLAB Answers post:
https://www.mathworks.com/matlabcentral/answers/518421-which-versions-of-xilinx-vivado-are-supported-with-which-release-of-hdl-coder
MATLAB R2023a (or later) should support Vivado 2022.1 (or later). Why does the example not work?I am trying to follow the HDL Coder demo "DAC and ADC Loopback Data Capture" for my ZCU111 board using MATLAB R2023a (or later) and Xilinx Vivado 2022.1 (or later):
https://www.mathworks.com/help/hdlcoder/ug/hdl-dac-adc-loopback-data-capture.html
The demo uses the "Real ADC/DAC Interface" reference design, as specified in step 1.2 in the HDL Workflow Advisor.
However, I encounter errors similar to the following at step 4.1 in the HDL Workflow Advisor:
The following IPs are not found in the IP Catalog:
xilinx.com:ip:usp_rf_data_converter:2.4
ERROR: [BD 5-216] VLNV <xilinx.com:ip:usp_rf_data_converter:2.4> is not supported for the current part.
The latest supported version for this part is: <2.5>
Based on the following MATLAB Answers post:
https://www.mathworks.com/matlabcentral/answers/518421-which-versions-of-xilinx-vivado-are-supported-with-which-release-of-hdl-coder
MATLAB R2023a (or later) should support Vivado 2022.1 (or later). Why does the example not work? I am trying to follow the HDL Coder demo "DAC and ADC Loopback Data Capture" for my ZCU111 board using MATLAB R2023a (or later) and Xilinx Vivado 2022.1 (or later):
https://www.mathworks.com/help/hdlcoder/ug/hdl-dac-adc-loopback-data-capture.html
The demo uses the "Real ADC/DAC Interface" reference design, as specified in step 1.2 in the HDL Workflow Advisor.
However, I encounter errors similar to the following at step 4.1 in the HDL Workflow Advisor:
The following IPs are not found in the IP Catalog:
xilinx.com:ip:usp_rf_data_converter:2.4
ERROR: [BD 5-216] VLNV <xilinx.com:ip:usp_rf_data_converter:2.4> is not supported for the current part.
The latest supported version for this part is: <2.5>
Based on the following MATLAB Answers post:
https://www.mathworks.com/matlabcentral/answers/518421-which-versions-of-xilinx-vivado-are-supported-with-which-release-of-hdl-coder
MATLAB R2023a (or later) should support Vivado 2022.1 (or later). Why does the example not work? vivado, dac, adc, ip, core MATLAB Answers — New Questions