Error using CosimWizardPkg.CosimWizardData/populateHdlHierarchy
I uses cosimulationConfiguration to create a HDL cosimulation block.
I get the following errors
Error using CosimWizardPkg.CosimWizardData/populateHdlHierarchy
Socket connection was closed by the other side
Error in CosimWizardPkg.CosimWizardData/autoFillAllModulesParameters
Error in CosimWizardPkg.ModuleSelection/onNext
Error in CosimWizardPkg.CosimWizardDlg/onNext
Error in cosimulationConfiguration/l_Step4
Error in cosimulationConfiguration/runWorkflow
Error in CosimCommandLineSimulink (line 56)
runWorkflow(c);
Scripts are as follows
%% CosimCommandLineSimulink.m
%% Configure Cosimulation Workflow
% Create a cosimulation configuration object.
%%
c = cosimulationConfiguration(‘Xcelium’,’Simulink’,’top’);
%%
% Set up the HDL file.
%%
c.HDLFiles = {…
‘./src/top.v’, ‘Verilog’,…
‘./src/model.v’, ‘Verilog’,…
};
%%
% Compilation Command
%%
c.HDLCompilationCommand ="xmsc -64bit ./src/model.cpp;" + …
"xmvlog -64bit ./src/top.v ./src/model.v;" + …
"g++ -m64 -o model.o -DNCSC -DCADENCE -D_GLIBCXX_USE_CXX11_ABI=1 " + …
"-DLNX86 -I -I /tools/cds/xceliummain_22.09.004_Linux//tools/systemc/include_pch/64bit " + …
"-I ${TOOL_PATH}/tools/systemc/include/ " + …
"-I ${TOOL_PATH}/tools.lnx86/include " + …
"-I ${TOOL_PATH}/tools/tbsc/include " + …
"-I ${TOOL_PATH}/tools/vic/include " + …
"-c -Wall ./src/*.cpp -fPIC;"+ …
"g++ -m64 -shared -Wl,-G "+ …
"-o systemc.so *.o "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoSim_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoroutines_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libsystemc_sh.so;"+ …
"g++ -m64 -shared -Wl,-G "+ …
"-o systemc.so *.o "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoSim_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoroutines_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libsystemc_sh.so";
%%
% Elaboration
%%
c.HDLElaborationOptions = ‘-64bit -access +wc -messages -loadsc ${PATH}/systemc’;
%%
% Set the clock to a period of 20 ns, and set the reset duration to 15 ns.
%%
specifyClock(c,’clk’,Period=20)
specifyReset(c,’reset’,Duration=15)
specifyInput(c,{‘clk_enable’,’data’,’inv’});
specifyOutput(c,{‘out’});
%%
% Display the port table. It reflects the
% settings just made for output, clock, and reset attributes. The other
% design ports will take on default attributes.
%%
portInterface(c);
%% Generate HDL Cosimulation Block
% Run the workflow to generate an HDL Cosimulation block and the
% accompanying files.
%%
runWorkflow(c);
Complete output when running CosimCommandLineSimulink.m
>> CosimCommandLineSimulink
—– Input Data Ports —–
3×1 table
Name
______________
{‘clk_enable’}
{‘data’ }
{‘inv’ }
—– Output Data Ports —–
2×5 table
Name SampleTime DataType Signed FractionLength
_____________________________ __________ ___________ ______ ______________
{‘default_output_definition’} 1 {‘Inherit’} true 0
{‘out’ } 1 {‘Inherit’} true 0
—– Clock Ports —–
2×3 table
Name Edge Period
____________________________ __________ ______
{‘default_clock_definition’} {‘Rising’} 10
{‘clk’ } {‘Rising’} 20
—– Reset Ports —–
2×3 table
Name InitialValue Duration
____________________________ ____________ ________
{‘default_reset_definition’} 1 8
{‘reset’ } 1 15
—– Unused Ports —–
0×1 empty table
——————– Step 1——————
Select the type of cosimulation you want to do. If the HDL simulator executable you want to use is not on the system path in your environment, you must specify its location.
——————– Step 2——————
Add all VHDL, Verilog, and/or script files to be used in cosimulation to the following table. If the file type cannot be automatically detected or the detection result is incorrect, specify the correct file type in the table. If possible, we will determine the compilation order automatically using HDL simulator provided functionality. Then the HDL files can be added in any order.
——————– Step 3——————
HDL Verifier has automatically generated the following HDL compilation commands. You can customize these commands with optional parameters as specified in the HDL simulator documentation but they are sufficient as shown to compile your HDL code for cosimulation. The HDL files will be compiled when you click Next.
Compiling HDL files. Please wait …
### Compiling HDL design
xmsc(64): 22.09-s004: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
xmsc: [TOOL PATH]/tools/cdsgcc/gcc/9.3/bin/g++ -DNCSC -DCADENCE -DLNX86 -D_GLIBCXX_USE_CXX11_ABI=1 -I[TOOL PATH]/systemc/include_pch/64bit -I[TOOL PATH]/tools/systemc/include/tlm2 -I[TOOL PATH]/tools/systemc/include/cci -I[TOOL PATH]/tools/tbsc/include -I[TOOL PATH]/tools/vic/include -c -Wall ./src/model.cpp
xmvlog(64): 22.09-s004: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
g++: warning: [TOOL PATH]/tools/systemc/include_pch/64bit: linker input file unused because linking not done
…done
——————– Step 4——————
Specify the name of the HDL module for cosimulation. The Cosimulation Wizard will launch the HDL simulator, load the specified module, and populate the port list of that HDL module before the next step. Use "Shared Memory" communication method if your firewall policy does not allow TCP/IP socket communication.
Elaborating and Loading HDL simulation image. Please wait …
### Elaborating HDL design
### Elaboration command: xmelab -64bit -access +wc -messages -loadsc [PATH]/systemc top
xmelab(64): 22.09-s004: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
Elaborating the design hierarchy:
Caching library ‘worklib’ ……. Done
The SystemC(r) Code included in this Product is Copyright 1996 – 2016 by all Contributors. All rights reserved.
The SystemC Code included in this Product has been modified by Cadence Design Systems, Inc. and CoWare, Inc. All such modifications are Copyright (c) 2004-2016 Cadence Design Systems, Inc. and Copyright (c) 2004 CoWare, Inc. All Rights Reserved.
SystemC(r) is a registered trademark of Accellera Systems Initiative, Inc. in the United States and other countries and is used with permission.
Building instance overlay tables: ……………….. Done
Building instance specific data structures.
Loading native compiled code: ……………….. Done
Design hierarchy summary:
Instances Unique
Modules: 2 2
Scalar wires: 6 –
Simulation timescale: 1ns
SystemC Design Summary:
Instances
sc_modules: 1
sc_ports: 5
sc_methods: 1
Writing initial simulation snapshot: worklib.top:module
Waiting for HDL Simulator to startup …
120 seconds to time-out …
To stop this process, press Ctrl+C in MATLAB console.
Waiting for HDL Simulator to startup …
119 seconds to time-out …
To stop this process, press Ctrl+C in MATLAB console.
…done
Error using CosimWizardPkg.CosimWizardData/populateHdlHierarchy
Socket connection was closed by the other side
Error in CosimWizardPkg.CosimWizardData/autoFillAllModulesParameters
Error in CosimWizardPkg.ModuleSelection/onNext
Error in CosimWizardPkg.CosimWizardDlg/onNext
Error in cosimulationConfiguration/l_Step4
Error in cosimulationConfiguration/runWorkflow
Error in CosimCommandLineSimulink (line 56)
runWorkflow(c);
Do you have any idea what is reason?
Note: paths of tools and files are hidden in this question.I uses cosimulationConfiguration to create a HDL cosimulation block.
I get the following errors
Error using CosimWizardPkg.CosimWizardData/populateHdlHierarchy
Socket connection was closed by the other side
Error in CosimWizardPkg.CosimWizardData/autoFillAllModulesParameters
Error in CosimWizardPkg.ModuleSelection/onNext
Error in CosimWizardPkg.CosimWizardDlg/onNext
Error in cosimulationConfiguration/l_Step4
Error in cosimulationConfiguration/runWorkflow
Error in CosimCommandLineSimulink (line 56)
runWorkflow(c);
Scripts are as follows
%% CosimCommandLineSimulink.m
%% Configure Cosimulation Workflow
% Create a cosimulation configuration object.
%%
c = cosimulationConfiguration(‘Xcelium’,’Simulink’,’top’);
%%
% Set up the HDL file.
%%
c.HDLFiles = {…
‘./src/top.v’, ‘Verilog’,…
‘./src/model.v’, ‘Verilog’,…
};
%%
% Compilation Command
%%
c.HDLCompilationCommand ="xmsc -64bit ./src/model.cpp;" + …
"xmvlog -64bit ./src/top.v ./src/model.v;" + …
"g++ -m64 -o model.o -DNCSC -DCADENCE -D_GLIBCXX_USE_CXX11_ABI=1 " + …
"-DLNX86 -I -I /tools/cds/xceliummain_22.09.004_Linux//tools/systemc/include_pch/64bit " + …
"-I ${TOOL_PATH}/tools/systemc/include/ " + …
"-I ${TOOL_PATH}/tools.lnx86/include " + …
"-I ${TOOL_PATH}/tools/tbsc/include " + …
"-I ${TOOL_PATH}/tools/vic/include " + …
"-c -Wall ./src/*.cpp -fPIC;"+ …
"g++ -m64 -shared -Wl,-G "+ …
"-o systemc.so *.o "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoSim_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoroutines_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libsystemc_sh.so;"+ …
"g++ -m64 -shared -Wl,-G "+ …
"-o systemc.so *.o "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoSim_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoroutines_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libsystemc_sh.so";
%%
% Elaboration
%%
c.HDLElaborationOptions = ‘-64bit -access +wc -messages -loadsc ${PATH}/systemc’;
%%
% Set the clock to a period of 20 ns, and set the reset duration to 15 ns.
%%
specifyClock(c,’clk’,Period=20)
specifyReset(c,’reset’,Duration=15)
specifyInput(c,{‘clk_enable’,’data’,’inv’});
specifyOutput(c,{‘out’});
%%
% Display the port table. It reflects the
% settings just made for output, clock, and reset attributes. The other
% design ports will take on default attributes.
%%
portInterface(c);
%% Generate HDL Cosimulation Block
% Run the workflow to generate an HDL Cosimulation block and the
% accompanying files.
%%
runWorkflow(c);
Complete output when running CosimCommandLineSimulink.m
>> CosimCommandLineSimulink
—– Input Data Ports —–
3×1 table
Name
______________
{‘clk_enable’}
{‘data’ }
{‘inv’ }
—– Output Data Ports —–
2×5 table
Name SampleTime DataType Signed FractionLength
_____________________________ __________ ___________ ______ ______________
{‘default_output_definition’} 1 {‘Inherit’} true 0
{‘out’ } 1 {‘Inherit’} true 0
—– Clock Ports —–
2×3 table
Name Edge Period
____________________________ __________ ______
{‘default_clock_definition’} {‘Rising’} 10
{‘clk’ } {‘Rising’} 20
—– Reset Ports —–
2×3 table
Name InitialValue Duration
____________________________ ____________ ________
{‘default_reset_definition’} 1 8
{‘reset’ } 1 15
—– Unused Ports —–
0×1 empty table
——————– Step 1——————
Select the type of cosimulation you want to do. If the HDL simulator executable you want to use is not on the system path in your environment, you must specify its location.
——————– Step 2——————
Add all VHDL, Verilog, and/or script files to be used in cosimulation to the following table. If the file type cannot be automatically detected or the detection result is incorrect, specify the correct file type in the table. If possible, we will determine the compilation order automatically using HDL simulator provided functionality. Then the HDL files can be added in any order.
——————– Step 3——————
HDL Verifier has automatically generated the following HDL compilation commands. You can customize these commands with optional parameters as specified in the HDL simulator documentation but they are sufficient as shown to compile your HDL code for cosimulation. The HDL files will be compiled when you click Next.
Compiling HDL files. Please wait …
### Compiling HDL design
xmsc(64): 22.09-s004: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
xmsc: [TOOL PATH]/tools/cdsgcc/gcc/9.3/bin/g++ -DNCSC -DCADENCE -DLNX86 -D_GLIBCXX_USE_CXX11_ABI=1 -I[TOOL PATH]/systemc/include_pch/64bit -I[TOOL PATH]/tools/systemc/include/tlm2 -I[TOOL PATH]/tools/systemc/include/cci -I[TOOL PATH]/tools/tbsc/include -I[TOOL PATH]/tools/vic/include -c -Wall ./src/model.cpp
xmvlog(64): 22.09-s004: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
g++: warning: [TOOL PATH]/tools/systemc/include_pch/64bit: linker input file unused because linking not done
…done
——————– Step 4——————
Specify the name of the HDL module for cosimulation. The Cosimulation Wizard will launch the HDL simulator, load the specified module, and populate the port list of that HDL module before the next step. Use "Shared Memory" communication method if your firewall policy does not allow TCP/IP socket communication.
Elaborating and Loading HDL simulation image. Please wait …
### Elaborating HDL design
### Elaboration command: xmelab -64bit -access +wc -messages -loadsc [PATH]/systemc top
xmelab(64): 22.09-s004: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
Elaborating the design hierarchy:
Caching library ‘worklib’ ……. Done
The SystemC(r) Code included in this Product is Copyright 1996 – 2016 by all Contributors. All rights reserved.
The SystemC Code included in this Product has been modified by Cadence Design Systems, Inc. and CoWare, Inc. All such modifications are Copyright (c) 2004-2016 Cadence Design Systems, Inc. and Copyright (c) 2004 CoWare, Inc. All Rights Reserved.
SystemC(r) is a registered trademark of Accellera Systems Initiative, Inc. in the United States and other countries and is used with permission.
Building instance overlay tables: ……………….. Done
Building instance specific data structures.
Loading native compiled code: ……………….. Done
Design hierarchy summary:
Instances Unique
Modules: 2 2
Scalar wires: 6 –
Simulation timescale: 1ns
SystemC Design Summary:
Instances
sc_modules: 1
sc_ports: 5
sc_methods: 1
Writing initial simulation snapshot: worklib.top:module
Waiting for HDL Simulator to startup …
120 seconds to time-out …
To stop this process, press Ctrl+C in MATLAB console.
Waiting for HDL Simulator to startup …
119 seconds to time-out …
To stop this process, press Ctrl+C in MATLAB console.
…done
Error using CosimWizardPkg.CosimWizardData/populateHdlHierarchy
Socket connection was closed by the other side
Error in CosimWizardPkg.CosimWizardData/autoFillAllModulesParameters
Error in CosimWizardPkg.ModuleSelection/onNext
Error in CosimWizardPkg.CosimWizardDlg/onNext
Error in cosimulationConfiguration/l_Step4
Error in cosimulationConfiguration/runWorkflow
Error in CosimCommandLineSimulink (line 56)
runWorkflow(c);
Do you have any idea what is reason?
Note: paths of tools and files are hidden in this question. I uses cosimulationConfiguration to create a HDL cosimulation block.
I get the following errors
Error using CosimWizardPkg.CosimWizardData/populateHdlHierarchy
Socket connection was closed by the other side
Error in CosimWizardPkg.CosimWizardData/autoFillAllModulesParameters
Error in CosimWizardPkg.ModuleSelection/onNext
Error in CosimWizardPkg.CosimWizardDlg/onNext
Error in cosimulationConfiguration/l_Step4
Error in cosimulationConfiguration/runWorkflow
Error in CosimCommandLineSimulink (line 56)
runWorkflow(c);
Scripts are as follows
%% CosimCommandLineSimulink.m
%% Configure Cosimulation Workflow
% Create a cosimulation configuration object.
%%
c = cosimulationConfiguration(‘Xcelium’,’Simulink’,’top’);
%%
% Set up the HDL file.
%%
c.HDLFiles = {…
‘./src/top.v’, ‘Verilog’,…
‘./src/model.v’, ‘Verilog’,…
};
%%
% Compilation Command
%%
c.HDLCompilationCommand ="xmsc -64bit ./src/model.cpp;" + …
"xmvlog -64bit ./src/top.v ./src/model.v;" + …
"g++ -m64 -o model.o -DNCSC -DCADENCE -D_GLIBCXX_USE_CXX11_ABI=1 " + …
"-DLNX86 -I -I /tools/cds/xceliummain_22.09.004_Linux//tools/systemc/include_pch/64bit " + …
"-I ${TOOL_PATH}/tools/systemc/include/ " + …
"-I ${TOOL_PATH}/tools.lnx86/include " + …
"-I ${TOOL_PATH}/tools/tbsc/include " + …
"-I ${TOOL_PATH}/tools/vic/include " + …
"-c -Wall ./src/*.cpp -fPIC;"+ …
"g++ -m64 -shared -Wl,-G "+ …
"-o systemc.so *.o "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoSim_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoroutines_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libsystemc_sh.so;"+ …
"g++ -m64 -shared -Wl,-G "+ …
"-o systemc.so *.o "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoSim_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libncscCoroutines_sh.so "+ …
"${TOOL_PATH}/tools/systemc/lib/64bit/libsystemc_sh.so";
%%
% Elaboration
%%
c.HDLElaborationOptions = ‘-64bit -access +wc -messages -loadsc ${PATH}/systemc’;
%%
% Set the clock to a period of 20 ns, and set the reset duration to 15 ns.
%%
specifyClock(c,’clk’,Period=20)
specifyReset(c,’reset’,Duration=15)
specifyInput(c,{‘clk_enable’,’data’,’inv’});
specifyOutput(c,{‘out’});
%%
% Display the port table. It reflects the
% settings just made for output, clock, and reset attributes. The other
% design ports will take on default attributes.
%%
portInterface(c);
%% Generate HDL Cosimulation Block
% Run the workflow to generate an HDL Cosimulation block and the
% accompanying files.
%%
runWorkflow(c);
Complete output when running CosimCommandLineSimulink.m
>> CosimCommandLineSimulink
—– Input Data Ports —–
3×1 table
Name
______________
{‘clk_enable’}
{‘data’ }
{‘inv’ }
—– Output Data Ports —–
2×5 table
Name SampleTime DataType Signed FractionLength
_____________________________ __________ ___________ ______ ______________
{‘default_output_definition’} 1 {‘Inherit’} true 0
{‘out’ } 1 {‘Inherit’} true 0
—– Clock Ports —–
2×3 table
Name Edge Period
____________________________ __________ ______
{‘default_clock_definition’} {‘Rising’} 10
{‘clk’ } {‘Rising’} 20
—– Reset Ports —–
2×3 table
Name InitialValue Duration
____________________________ ____________ ________
{‘default_reset_definition’} 1 8
{‘reset’ } 1 15
—– Unused Ports —–
0×1 empty table
——————– Step 1——————
Select the type of cosimulation you want to do. If the HDL simulator executable you want to use is not on the system path in your environment, you must specify its location.
——————– Step 2——————
Add all VHDL, Verilog, and/or script files to be used in cosimulation to the following table. If the file type cannot be automatically detected or the detection result is incorrect, specify the correct file type in the table. If possible, we will determine the compilation order automatically using HDL simulator provided functionality. Then the HDL files can be added in any order.
——————– Step 3——————
HDL Verifier has automatically generated the following HDL compilation commands. You can customize these commands with optional parameters as specified in the HDL simulator documentation but they are sufficient as shown to compile your HDL code for cosimulation. The HDL files will be compiled when you click Next.
Compiling HDL files. Please wait …
### Compiling HDL design
xmsc(64): 22.09-s004: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
xmsc: [TOOL PATH]/tools/cdsgcc/gcc/9.3/bin/g++ -DNCSC -DCADENCE -DLNX86 -D_GLIBCXX_USE_CXX11_ABI=1 -I[TOOL PATH]/systemc/include_pch/64bit -I[TOOL PATH]/tools/systemc/include/tlm2 -I[TOOL PATH]/tools/systemc/include/cci -I[TOOL PATH]/tools/tbsc/include -I[TOOL PATH]/tools/vic/include -c -Wall ./src/model.cpp
xmvlog(64): 22.09-s004: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
g++: warning: [TOOL PATH]/tools/systemc/include_pch/64bit: linker input file unused because linking not done
…done
——————– Step 4——————
Specify the name of the HDL module for cosimulation. The Cosimulation Wizard will launch the HDL simulator, load the specified module, and populate the port list of that HDL module before the next step. Use "Shared Memory" communication method if your firewall policy does not allow TCP/IP socket communication.
Elaborating and Loading HDL simulation image. Please wait …
### Elaborating HDL design
### Elaboration command: xmelab -64bit -access +wc -messages -loadsc [PATH]/systemc top
xmelab(64): 22.09-s004: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
Elaborating the design hierarchy:
Caching library ‘worklib’ ……. Done
The SystemC(r) Code included in this Product is Copyright 1996 – 2016 by all Contributors. All rights reserved.
The SystemC Code included in this Product has been modified by Cadence Design Systems, Inc. and CoWare, Inc. All such modifications are Copyright (c) 2004-2016 Cadence Design Systems, Inc. and Copyright (c) 2004 CoWare, Inc. All Rights Reserved.
SystemC(r) is a registered trademark of Accellera Systems Initiative, Inc. in the United States and other countries and is used with permission.
Building instance overlay tables: ……………….. Done
Building instance specific data structures.
Loading native compiled code: ……………….. Done
Design hierarchy summary:
Instances Unique
Modules: 2 2
Scalar wires: 6 –
Simulation timescale: 1ns
SystemC Design Summary:
Instances
sc_modules: 1
sc_ports: 5
sc_methods: 1
Writing initial simulation snapshot: worklib.top:module
Waiting for HDL Simulator to startup …
120 seconds to time-out …
To stop this process, press Ctrl+C in MATLAB console.
Waiting for HDL Simulator to startup …
119 seconds to time-out …
To stop this process, press Ctrl+C in MATLAB console.
…done
Error using CosimWizardPkg.CosimWizardData/populateHdlHierarchy
Socket connection was closed by the other side
Error in CosimWizardPkg.CosimWizardData/autoFillAllModulesParameters
Error in CosimWizardPkg.ModuleSelection/onNext
Error in CosimWizardPkg.CosimWizardDlg/onNext
Error in cosimulationConfiguration/l_Step4
Error in cosimulationConfiguration/runWorkflow
Error in CosimCommandLineSimulink (line 56)
runWorkflow(c);
Do you have any idea what is reason?
Note: paths of tools and files are hidden in this question. hdlverifier, cosimulationconfiguration, simulink, cadence, xcelium MATLAB Answers — New Questions