I have a custom cyclone v soc board. I’m trying to follow along with debug IP core using FPGA Data Capture. https://www.mathworks.com/help/hdlcoder/ug/debug-ip-core-using-fpga-data-capture.html . The FPGA Data Capture interface does not appear for me as shown in step 1.2 of HDL Workflow Advisor. How do I add this interface to my custom reference design. Will HDL Workflow Advisor automatically add the appropriate IP core to the qsys project based on what signals I want to log?

I think part of the problem is I don’t have any FDC block in my library:

As you can see I do have the HDL Verifier Support Package for Intel Boards installed but there is no FPGA Data Capture block. I can not find it when searching for it either. Does this block exist in some other package or is there something wrong with my install?I have a custom cyclone v soc board. I’m trying to follow along with debug IP core using FPGA Data Capture. https://www.mathworks.com/help/hdlcoder/ug/debug-ip-core-using-fpga-data-capture.html . The FPGA Data Capture interface does not appear for me as shown in step 1.2 of HDL Workflow Advisor. How do I add this interface to my custom reference design. Will HDL Workflow Advisor automatically add the appropriate IP core to the qsys project based on what signals I want to log?

I think part of the problem is I don’t have any FDC block in my library:

As you can see I do have the HDL Verifier Support Package for Intel Boards installed but there is no FPGA Data Capture block. I can not find it when searching for it either. Does this block exist in some other package or is there something wrong with my install? I have a custom cyclone v soc board. I’m trying to follow along with debug IP core using FPGA Data Capture. https://www.mathworks.com/help/hdlcoder/ug/debug-ip-core-using-fpga-data-capture.html . The FPGA Data Capture interface does not appear for me as shown in step 1.2 of HDL Workflow Advisor. How do I add this interface to my custom reference design. Will HDL Workflow Advisor automatically add the appropriate IP core to the qsys project based on what signals I want to log?

I think part of the problem is I don’t have any FDC block in my library:

As you can see I do have the HDL Verifier Support Package for Intel Boards installed but there is no FPGA Data Capture block. I can not find it when searching for it either. Does this block exist in some other package or is there something wrong with my install? hdl verifier MATLAB Answers — New Questions

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