Hi Kiran
Hope you doing well. I have seen your helpful answers for everyone. However , i have an issue and wish if you can help. I am trying to generate a PWM pulses using Speedgoat model IO334 FPGA. I have to customise an up-down counter ( as a carrier) to compare with a reference signal in order to obtain our PWM signals to drive a convertor. This counter must be HDL supported.
Keywords : Clock cycle of the speed goat is 10 nanos . Resulation can be 2^32-1.
I will appreciate if you can helpHi Kiran
Hope you doing well. I have seen your helpful answers for everyone. However , i have an issue and wish if you can help. I am trying to generate a PWM pulses using Speedgoat model IO334 FPGA. I have to customise an up-down counter ( as a carrier) to compare with a reference signal in order to obtain our PWM signals to drive a convertor. This counter must be HDL supported.
Keywords : Clock cycle of the speed goat is 10 nanos . Resulation can be 2^32-1.
I will appreciate if you can help Hi Kiran
Hope you doing well. I have seen your helpful answers for everyone. However , i have an issue and wish if you can help. I am trying to generate a PWM pulses using Speedgoat model IO334 FPGA. I have to customise an up-down counter ( as a carrier) to compare with a reference signal in order to obtain our PWM signals to drive a convertor. This counter must be HDL supported.
Keywords : Clock cycle of the speed goat is 10 nanos . Resulation can be 2^32-1.
I will appreciate if you can help pwm, fpga MATLAB Answers — New Questions

​