HDL Coder and Bitstream Programming Insight Needed
I am trying to program the DAC PL-DDR Transmit example ( https://www.mathworks.com/help/hdlcoder/ug/hdl-dac-PL-DDR4-transmit.html ) to my ZCU216 board. I have already asked a question about this a few days ago but will make this one more broad to give it a better chance of being answered.
When generating and programming the bitstream, I ensure that the AXI4 Stream Interface is 128 bits wide. However, when I run the addAXI4StreamInterface() function, a prequisite to writing to the port from MATLAB for testing purposes, I am getting data mismatch errors that can be resolved by changing the inteface width to 64 bits. So, clearly the programmed FPGA is expecting the function to request 64 bits and not 128.
My question is: what kind of troubleshooting steps are aviailable for an issue like this? Trying to explore these functions, you run into .p files quickly, so it’s been impossible so far to see what’s going on under the hood.I am trying to program the DAC PL-DDR Transmit example ( https://www.mathworks.com/help/hdlcoder/ug/hdl-dac-PL-DDR4-transmit.html ) to my ZCU216 board. I have already asked a question about this a few days ago but will make this one more broad to give it a better chance of being answered.
When generating and programming the bitstream, I ensure that the AXI4 Stream Interface is 128 bits wide. However, when I run the addAXI4StreamInterface() function, a prequisite to writing to the port from MATLAB for testing purposes, I am getting data mismatch errors that can be resolved by changing the inteface width to 64 bits. So, clearly the programmed FPGA is expecting the function to request 64 bits and not 128.
My question is: what kind of troubleshooting steps are aviailable for an issue like this? Trying to explore these functions, you run into .p files quickly, so it’s been impossible so far to see what’s going on under the hood. I am trying to program the DAC PL-DDR Transmit example ( https://www.mathworks.com/help/hdlcoder/ug/hdl-dac-PL-DDR4-transmit.html ) to my ZCU216 board. I have already asked a question about this a few days ago but will make this one more broad to give it a better chance of being answered.
When generating and programming the bitstream, I ensure that the AXI4 Stream Interface is 128 bits wide. However, when I run the addAXI4StreamInterface() function, a prequisite to writing to the port from MATLAB for testing purposes, I am getting data mismatch errors that can be resolved by changing the inteface width to 64 bits. So, clearly the programmed FPGA is expecting the function to request 64 bits and not 128.
My question is: what kind of troubleshooting steps are aviailable for an issue like this? Trying to explore these functions, you run into .p files quickly, so it’s been impossible so far to see what’s going on under the hood. hdl coder, zcu216, dac, ddr MATLAB Answers — New Questions
