Dear all,

I am starting to use SoC Blockset add-on and now figuring out how RF Data Converter block works.
For example I set the following parameters in RF Data Converter:

(Sample rate 1024 MSPS, Interpolation/Decimation 1, Samples per clock cycle 4 –> Stream Clock Frequency 256MHz)
The FPGA sampling time is also set to 7.1825e-9 to correspond to Stream Clock Frequency of 256MHz.
Then, in the timing manager we can see, that the RF Data Converter transmits (updates the output dacTxChy) with Stream Clock Frequency of 256MHz.

Now we can set Interpolation/Decimation to 2 (This changes Stream Clock Frequency to 128MHz. The FPGA sampling time is unchanged.
We can now see, that RF Data Converter updates the output dacTxChy with Stream Clock Frequency of 128MHz. This "eats" some of the FPGA samples, which is bad, so I am not sure this is how I should use this block.

The question is what Interpolation setting is done for and how to apply it? Is this ok that when I set the Interpolation parameter to the value different from 1 it seems like the actual sampling frequency just decreases without any benefits? Why not then just decrease Sample rate of RF Data Converter? Thank you!Dear all,

I am starting to use SoC Blockset add-on and now figuring out how RF Data Converter block works.
For example I set the following parameters in RF Data Converter:

(Sample rate 1024 MSPS, Interpolation/Decimation 1, Samples per clock cycle 4 –> Stream Clock Frequency 256MHz)
The FPGA sampling time is also set to 7.1825e-9 to correspond to Stream Clock Frequency of 256MHz.
Then, in the timing manager we can see, that the RF Data Converter transmits (updates the output dacTxChy) with Stream Clock Frequency of 256MHz.

Now we can set Interpolation/Decimation to 2 (This changes Stream Clock Frequency to 128MHz. The FPGA sampling time is unchanged.
We can now see, that RF Data Converter updates the output dacTxChy with Stream Clock Frequency of 128MHz. This "eats" some of the FPGA samples, which is bad, so I am not sure this is how I should use this block.

The question is what Interpolation setting is done for and how to apply it? Is this ok that when I set the Interpolation parameter to the value different from 1 it seems like the actual sampling frequency just decreases without any benefits? Why not then just decrease Sample rate of RF Data Converter? Thank you! Dear all,

I am starting to use SoC Blockset add-on and now figuring out how RF Data Converter block works.
For example I set the following parameters in RF Data Converter:

(Sample rate 1024 MSPS, Interpolation/Decimation 1, Samples per clock cycle 4 –> Stream Clock Frequency 256MHz)
The FPGA sampling time is also set to 7.1825e-9 to correspond to Stream Clock Frequency of 256MHz.
Then, in the timing manager we can see, that the RF Data Converter transmits (updates the output dacTxChy) with Stream Clock Frequency of 256MHz.

Now we can set Interpolation/Decimation to 2 (This changes Stream Clock Frequency to 128MHz. The FPGA sampling time is unchanged.
We can now see, that RF Data Converter updates the output dacTxChy with Stream Clock Frequency of 128MHz. This "eats" some of the FPGA samples, which is bad, so I am not sure this is how I should use this block.

The question is what Interpolation setting is done for and how to apply it? Is this ok that when I set the Interpolation parameter to the value different from 1 it seems like the actual sampling frequency just decreases without any benefits? Why not then just decrease Sample rate of RF Data Converter? Thank you! soc blockset, rf data converter, sampling frequency, interpolation, clocking, fpga, dac, adc MATLAB Answers — New Questions

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