How can I change the default axi width in VCK190 reference file from 32 to 64 bits?
I am trying to build IP using the provided VCK190 SoC template. However, the maximum allowed AXI width from software to the FPGA is 32 bits which is very low. I need 64 bits or higher. Where can I go to change this in the reference design?I am trying to build IP using the provided VCK190 SoC template. However, the maximum allowed AXI width from software to the FPGA is 32 bits which is very low. I need 64 bits or higher. Where can I go to change this in the reference design? I am trying to build IP using the provided VCK190 SoC template. However, the maximum allowed AXI width from software to the FPGA is 32 bits which is very low. I need 64 bits or higher. Where can I go to change this in the reference design? hdl coder, soc, axi width MATLAB Answers — New Questions
