I’m quite new to this, but I’d like to generate a custom deep learning processor IP core using a specific board, the Terasic DE-1 SoC, with Deep Learning HDL Toolbox.
I’ve found documentation on how to create a general custom board reference (https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-intel-soc-workflow.html) and how to generate a deep learning processor IP Core (https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html), but I’m unsure about configuration of the AXI-4 interfaces. Would I even be able to do this on this particular board? Would it utilize using Quartus first to further configure something?I’m quite new to this, but I’d like to generate a custom deep learning processor IP core using a specific board, the Terasic DE-1 SoC, with Deep Learning HDL Toolbox.
I’ve found documentation on how to create a general custom board reference (https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-intel-soc-workflow.html) and how to generate a deep learning processor IP Core (https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html), but I’m unsure about configuration of the AXI-4 interfaces. Would I even be able to do this on this particular board? Would it utilize using Quartus first to further configure something? I’m quite new to this, but I’d like to generate a custom deep learning processor IP core using a specific board, the Terasic DE-1 SoC, with Deep Learning HDL Toolbox.
I’ve found documentation on how to create a general custom board reference (https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-intel-soc-workflow.html) and how to generate a deep learning processor IP Core (https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html), but I’m unsure about configuration of the AXI-4 interfaces. Would I even be able to do this on this particular board? Would it utilize using Quartus first to further configure something? neural networks, code generation, fpga MATLAB Answers — New Questions

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