Hi,
I’m currently working with the Deep Learning HDL Toolbox and would like to integrate the generated IP core into my own RTL design.
I used Wireshark to capture the traffic between MATLAB and the board, and I can now “run” the core by replaying those packets.
However, I haven’t been able to reverse-engineer the full initialization sequence: loading the network weights into external DDR, programming the configuration registers, and completing any hidden hand-shakes that happen before the first inference.
When I let MATLAB drive the board the same bit-stream works perfectly, so the missing piece is clearly the initialization flow.
Could you point me to the register map, the required power-on sequence, or any documentation that explains how to bring the Deep Learning IP out of reset and validate that it is ready to accept input data?
Thank you very much for your help.
Best regards.
Looking forward to your reply.Hi,
I’m currently working with the Deep Learning HDL Toolbox and would like to integrate the generated IP core into my own RTL design.
I used Wireshark to capture the traffic between MATLAB and the board, and I can now “run” the core by replaying those packets.
However, I haven’t been able to reverse-engineer the full initialization sequence: loading the network weights into external DDR, programming the configuration registers, and completing any hidden hand-shakes that happen before the first inference.
When I let MATLAB drive the board the same bit-stream works perfectly, so the missing piece is clearly the initialization flow.
Could you point me to the register map, the required power-on sequence, or any documentation that explains how to bring the Deep Learning IP out of reset and validate that it is ready to accept input data?
Thank you very much for your help.
Best regards.
Looking forward to your reply. Hi,
I’m currently working with the Deep Learning HDL Toolbox and would like to integrate the generated IP core into my own RTL design.
I used Wireshark to capture the traffic between MATLAB and the board, and I can now “run” the core by replaying those packets.
However, I haven’t been able to reverse-engineer the full initialization sequence: loading the network weights into external DDR, programming the configuration registers, and completing any hidden hand-shakes that happen before the first inference.
When I let MATLAB drive the board the same bit-stream works perfectly, so the missing piece is clearly the initialization flow.
Could you point me to the register map, the required power-on sequence, or any documentation that explains how to bring the Deep Learning IP out of reset and validate that it is ready to accept input data?
Thank you very much for your help.
Best regards.
Looking forward to your reply. fpga, deep learning ip core, initialize MATLAB Answers — New Questions

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