I am using Speedgoat Performance P3 with IO334.
I have found an example demonstrating the use of Analog Interface (IO334_ad_da_hdlc.slx).
I have managed to generate HDL code and succesfully ran the model on Speedgoat. In this particular model the sine signals are supposed to be generated on the FPGA (there is internal sine generator inside DUT), send to AO channels and then routed by external wiring back to the AI channels.
However, I dont understand what kind of use is to loopback "data" and "trigger" label in IO334_ad_da_hdlc.slx. Input ports (AD_xx, AD_valid_X_X) and output ports (DA_xx, AD_Trigger_X_X) are mapped to the respective AI and AO interfaces via HDL advisor and external wiring connects signals from AOs to AIs. Can you clarify what is the purpose of this software loopback in the model?I am using Speedgoat Performance P3 with IO334.
I have found an example demonstrating the use of Analog Interface (IO334_ad_da_hdlc.slx).
I have managed to generate HDL code and succesfully ran the model on Speedgoat. In this particular model the sine signals are supposed to be generated on the FPGA (there is internal sine generator inside DUT), send to AO channels and then routed by external wiring back to the AI channels.
However, I dont understand what kind of use is to loopback "data" and "trigger" label in IO334_ad_da_hdlc.slx. Input ports (AD_xx, AD_valid_X_X) and output ports (DA_xx, AD_Trigger_X_X) are mapped to the respective AI and AO interfaces via HDL advisor and external wiring connects signals from AOs to AIs. Can you clarify what is the purpose of this software loopback in the model? I am using Speedgoat Performance P3 with IO334.
I have found an example demonstrating the use of Analog Interface (IO334_ad_da_hdlc.slx).
I have managed to generate HDL code and succesfully ran the model on Speedgoat. In this particular model the sine signals are supposed to be generated on the FPGA (there is internal sine generator inside DUT), send to AO channels and then routed by external wiring back to the AI channels.
However, I dont understand what kind of use is to loopback "data" and "trigger" label in IO334_ad_da_hdlc.slx. Input ports (AD_xx, AD_valid_X_X) and output ports (DA_xx, AD_Trigger_X_X) are mapped to the respective AI and AO interfaces via HDL advisor and external wiring connects signals from AOs to AIs. Can you clarify what is the purpose of this software loopback in the model? speedgoat, hdl coder, real-time MATLAB Answers — New Questions

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