In pwm_example_hdlc.slx example from Speedgoat Motion Control HDL I/O Blockset v1.0 (R2024b). I want to view logged signals in SDI. There are PWM and CAP signals in the example which are set to logging.
I succesfully generated bitstream and run example on Speedgoat P3 Perfomance. The hardware generates PWM signals as expected (confirmed with oscilloscope). However, the SDI does not have any signal available during or post model execution.
During model build the following warning(s) is issued:
Warning: Unable to instrument ‘gm_pwm_example_hdlc_slrt/DUT PWM and CAP/DataTypeConversion:1’: Unable to stream signal
‘gm_pwm_example_hdlc_slrt/DUT PWM and CAP/DataTypeConversion:1’. Possible reasons include:
(1) Signal is not available in application.
(2) Signal does not use globally accessible memory in application.
(3) Signal connects to a MessageSend block.
(4) Signal has inherited sample time.
(5) Signal is discontiguous.
For more suggestions to resolve this issue, see Troubleshoot Signals for Streaming or File Log logging.
I followed the advice given in Troubleshoot Signals for Streaming or File Log logging and in this post:
added test point
added Signal Copy Block
made PWM_A signal globally accessible
But the issue persist and no data appears in SDI (external mode, command line, slrtExplorer).
If I add the rate transition block, the signal appear in SDI, however the value is 0 (Output port sample time is 1e-4s), whereas PWM perion is 1e-3s.

If I add sine generator block in the model and log its output, this sine output signal appears in SDI as expected.
What can be the reason that the outputs from FPGA cannot be visualized in the model?In pwm_example_hdlc.slx example from Speedgoat Motion Control HDL I/O Blockset v1.0 (R2024b). I want to view logged signals in SDI. There are PWM and CAP signals in the example which are set to logging.
I succesfully generated bitstream and run example on Speedgoat P3 Perfomance. The hardware generates PWM signals as expected (confirmed with oscilloscope). However, the SDI does not have any signal available during or post model execution.
During model build the following warning(s) is issued:
Warning: Unable to instrument ‘gm_pwm_example_hdlc_slrt/DUT PWM and CAP/DataTypeConversion:1’: Unable to stream signal
‘gm_pwm_example_hdlc_slrt/DUT PWM and CAP/DataTypeConversion:1’. Possible reasons include:
(1) Signal is not available in application.
(2) Signal does not use globally accessible memory in application.
(3) Signal connects to a MessageSend block.
(4) Signal has inherited sample time.
(5) Signal is discontiguous.
For more suggestions to resolve this issue, see Troubleshoot Signals for Streaming or File Log logging.
I followed the advice given in Troubleshoot Signals for Streaming or File Log logging and in this post:
added test point
added Signal Copy Block
made PWM_A signal globally accessible
But the issue persist and no data appears in SDI (external mode, command line, slrtExplorer).
If I add the rate transition block, the signal appear in SDI, however the value is 0 (Output port sample time is 1e-4s), whereas PWM perion is 1e-3s.

If I add sine generator block in the model and log its output, this sine output signal appears in SDI as expected.
What can be the reason that the outputs from FPGA cannot be visualized in the model? In pwm_example_hdlc.slx example from Speedgoat Motion Control HDL I/O Blockset v1.0 (R2024b). I want to view logged signals in SDI. There are PWM and CAP signals in the example which are set to logging.
I succesfully generated bitstream and run example on Speedgoat P3 Perfomance. The hardware generates PWM signals as expected (confirmed with oscilloscope). However, the SDI does not have any signal available during or post model execution.
During model build the following warning(s) is issued:
Warning: Unable to instrument ‘gm_pwm_example_hdlc_slrt/DUT PWM and CAP/DataTypeConversion:1’: Unable to stream signal
‘gm_pwm_example_hdlc_slrt/DUT PWM and CAP/DataTypeConversion:1’. Possible reasons include:
(1) Signal is not available in application.
(2) Signal does not use globally accessible memory in application.
(3) Signal connects to a MessageSend block.
(4) Signal has inherited sample time.
(5) Signal is discontiguous.
For more suggestions to resolve this issue, see Troubleshoot Signals for Streaming or File Log logging.
I followed the advice given in Troubleshoot Signals for Streaming or File Log logging and in this post:
added test point
added Signal Copy Block
made PWM_A signal globally accessible
But the issue persist and no data appears in SDI (external mode, command line, slrtExplorer).
If I add the rate transition block, the signal appear in SDI, however the value is 0 (Output port sample time is 1e-4s), whereas PWM perion is 1e-3s.

If I add sine generator block in the model and log its output, this sine output signal appears in SDI as expected.
What can be the reason that the outputs from FPGA cannot be visualized in the model? real-time, speedgoat, sdi MATLAB Answers — New Questions

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