Why do I get the Xilinx Vivado error message “Specified part could not be found” during IP Core Generation with HDL Workflow Advisor or SoC Builder?
I am trying to generate an IP Core using HDL Coder. However, in step 3.2 of HDL Workflow Advisor, I see:
Failed Task "Vivado IP Packager" unsuccessful. See log for details. Generated logfile:
hdl_prjhdlsrcDUTnameworkflow_task_VivadoIPPackager.log
Error in hdlturnkey.ip.IPEmitterVivado/packageVivadoIP
Error in hdlturnkey.ip.IPDriver/generateIPCore
And the content in the "workflow_task_VivadoIPPackager.log" file is:
Task "Vivado IP Packager" unsuccessful. See log for details.
Generated logfile:
****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source vivado_ip_package.tcl -notrace
WARNING: [Device 21-436] No parts matched ‘xc7k325tffg900-2’
ERROR: [Coretcl 2-106] Specified part could not be found.
INFO: [Common 17-206] Exiting Vivado at Mon May 30 15:13:18 2022…
Elapsed time is 5.1019 seconds.
A log file with the same name containing the same error message may be created when using SoC Blockset and SoC Builder.I am trying to generate an IP Core using HDL Coder. However, in step 3.2 of HDL Workflow Advisor, I see:
Failed Task "Vivado IP Packager" unsuccessful. See log for details. Generated logfile:
hdl_prjhdlsrcDUTnameworkflow_task_VivadoIPPackager.log
Error in hdlturnkey.ip.IPEmitterVivado/packageVivadoIP
Error in hdlturnkey.ip.IPDriver/generateIPCore
And the content in the "workflow_task_VivadoIPPackager.log" file is:
Task "Vivado IP Packager" unsuccessful. See log for details.
Generated logfile:
****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source vivado_ip_package.tcl -notrace
WARNING: [Device 21-436] No parts matched ‘xc7k325tffg900-2’
ERROR: [Coretcl 2-106] Specified part could not be found.
INFO: [Common 17-206] Exiting Vivado at Mon May 30 15:13:18 2022…
Elapsed time is 5.1019 seconds.
A log file with the same name containing the same error message may be created when using SoC Blockset and SoC Builder. I am trying to generate an IP Core using HDL Coder. However, in step 3.2 of HDL Workflow Advisor, I see:
Failed Task "Vivado IP Packager" unsuccessful. See log for details. Generated logfile:
hdl_prjhdlsrcDUTnameworkflow_task_VivadoIPPackager.log
Error in hdlturnkey.ip.IPEmitterVivado/packageVivadoIP
Error in hdlturnkey.ip.IPDriver/generateIPCore
And the content in the "workflow_task_VivadoIPPackager.log" file is:
Task "Vivado IP Packager" unsuccessful. See log for details.
Generated logfile:
****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source vivado_ip_package.tcl -notrace
WARNING: [Device 21-436] No parts matched ‘xc7k325tffg900-2’
ERROR: [Coretcl 2-106] Specified part could not be found.
INFO: [Common 17-206] Exiting Vivado at Mon May 30 15:13:18 2022…
Elapsed time is 5.1019 seconds.
A log file with the same name containing the same error message may be created when using SoC Blockset and SoC Builder. MATLAB Answers — New Questions