Why do I receive a privimporthdl error when importing the operator.vhd example

Hello,
I am trying to import a VHDL file using the operator.vhd example. However, I receive the following error when using the importhdl function.

I beleive I have followed the example correctly, but I am at a loss as to why this is occuring. Is this a problem experienced by others at all? I’m not sure what I can try next.
Below is the operator.vhd code when it is opened within the MATLAB editor.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Operator is
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
OpSelect : in STD_LOGIC_VECTOR(2 downto 0);
Result : out STD_LOGIC_VECTOR(3 downto 0));
end Operator;

architecture Behavioral of Operator is
begin
process(A, B, OpSelect)
begin
case OpSelect is
when "000" => — Addition
Result <= A + B;
when "001" => — Subtraction
Result <= A – B;
when "010" => — Bitwise AND
Result <= A and B;
when "011" => — Bitwise OR
Result <= A or B;
when "100" => — Bitwise XOR
Result <= A xor B;
when others => — Default case
Result <= not (A + B);
end case;
end process;
end Behavioral;Hello,
I am trying to import a VHDL file using the operator.vhd example. However, I receive the following error when using the importhdl function.

architecture Behavioral of Operator is
begin
process(A, B, OpSelect)
begin
case OpSelect is
when "000" => — Addition
Result <= A + B;
when "001" => — Subtraction
Result <= A – B;
when "010" => — Bitwise AND
Result <= A and B;
when "011" => — Bitwise OR
Result <= A or B;
when "100" => — Bitwise XOR
Result <= A xor B;
when others => — Default case
Result <= not (A + B);
end case;
end process;
end Behavioral; Hello,
I am trying to import a VHDL file using the operator.vhd example. However, I receive the following error when using the importhdl function.

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