How to generate IP block from QAM receiver example?
I want to generate an IP block from the QAM receiver part from this example:
https://www.mathworks.com/help/comm/ug/hdl-optimized-qam-transmitter-and-receiver.html?searchHighlight=hdl%20qam64&s_tid=srchtitle_support_results_1_hdl%20qam64
To generate an IP core with AXI-stream slave interface using HDL coder it is necessary to specify the valid signal. I do not know what is the right approach to address this.
The model contains a rate transition (there is decimation filter in the Coarse Frequency
Offset Correction ) so it is not possible just wrap the whole system into one enabled subsystem, how it is suggested in this example:
https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html
How to handle the valid-in signal? Should I split the model to two (or more) enabled submodels before and after the rate transition? Should I manually downsample the valid signal using the downsample block and use the right number of delays to synchronize it?
Is the example just a demonstration of the HDL libraries that nobody intended to use for HDL code generation? What do I miss?I want to generate an IP block from the QAM receiver part from this example:
https://www.mathworks.com/help/comm/ug/hdl-optimized-qam-transmitter-and-receiver.html?searchHighlight=hdl%20qam64&s_tid=srchtitle_support_results_1_hdl%20qam64
To generate an IP core with AXI-stream slave interface using HDL coder it is necessary to specify the valid signal. I do not know what is the right approach to address this.
The model contains a rate transition (there is decimation filter in the Coarse Frequency
Offset Correction ) so it is not possible just wrap the whole system into one enabled subsystem, how it is suggested in this example:
https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html
How to handle the valid-in signal? Should I split the model to two (or more) enabled submodels before and after the rate transition? Should I manually downsample the valid signal using the downsample block and use the right number of delays to synchronize it?
Is the example just a demonstration of the HDL libraries that nobody intended to use for HDL code generation? What do I miss? I want to generate an IP block from the QAM receiver part from this example:
https://www.mathworks.com/help/comm/ug/hdl-optimized-qam-transmitter-and-receiver.html?searchHighlight=hdl%20qam64&s_tid=srchtitle_support_results_1_hdl%20qam64
To generate an IP core with AXI-stream slave interface using HDL coder it is necessary to specify the valid signal. I do not know what is the right approach to address this.
The model contains a rate transition (there is decimation filter in the Coarse Frequency
Offset Correction ) so it is not possible just wrap the whole system into one enabled subsystem, how it is suggested in this example:
https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html
How to handle the valid-in signal? Should I split the model to two (or more) enabled submodels before and after the rate transition? Should I manually downsample the valid signal using the downsample block and use the right number of delays to synchronize it?
Is the example just a demonstration of the HDL libraries that nobody intended to use for HDL code generation? What do I miss? qam, axi-stream, multirate, hdl coder, valid signal MATLAB Answers — New Questions