Hi, I am building a system to be deployed on an RFSoC. I have used serialize blocks on the processor to stream data through the memory using an Software to AXI4-Stream block to the Programmable Logic (PL).

Instead of using the serializer/deserializer block directly, I had to go to its library and copy its system to create a subsytem in my design containing it. That was needed because I had to access the rate transition blocks and change the parameter from "Multiple of input port sample time" to "inherit" – I did that because the system wouldn’t compile with the original parameter, throwing me the following error:
"Asynchronous sample time is found at input port 0 of Rate Transition block ‘path/to/subsystem/Serializer/rateTrans’. When Rate Transition block parameter ‘Output port sample time option’ is ‘Multiple of input port sample time’, asynchronous sample time is not allowed. Consider changing ‘Output port sample time option’ to "Specify" or "Inherit"."
I could overcome this error by changing the rate transition parameter and the model worked as expected during simulation.
When the data arrives to the PL, I need to deserialize it, which worked on simulation. However, during the build phase, I got the following error, which is rather unclear how to solve, once that the serializer/deserializer are supposed to be supported by HDL Coder.
"Compilation errors when generating code for: HDL1DDs Error during MATLAB code compilation: Error Path: /usr/local/MATLAB/R2022b/toolbox/shared/system/coder/+matlab/+system/+hdlcoder/System.p Error Location: (@Row: –> 1 @Column: –> 1) System object ‘hdl.deserializer1D’ is not supported for HDL code generation."

Can you help me find out what the problem is here? Thanks in advance.Hi, I am building a system to be deployed on an RFSoC. I have used serialize blocks on the processor to stream data through the memory using an Software to AXI4-Stream block to the Programmable Logic (PL).

Instead of using the serializer/deserializer block directly, I had to go to its library and copy its system to create a subsytem in my design containing it. That was needed because I had to access the rate transition blocks and change the parameter from "Multiple of input port sample time" to "inherit" – I did that because the system wouldn’t compile with the original parameter, throwing me the following error:
"Asynchronous sample time is found at input port 0 of Rate Transition block ‘path/to/subsystem/Serializer/rateTrans’. When Rate Transition block parameter ‘Output port sample time option’ is ‘Multiple of input port sample time’, asynchronous sample time is not allowed. Consider changing ‘Output port sample time option’ to "Specify" or "Inherit"."
I could overcome this error by changing the rate transition parameter and the model worked as expected during simulation.
When the data arrives to the PL, I need to deserialize it, which worked on simulation. However, during the build phase, I got the following error, which is rather unclear how to solve, once that the serializer/deserializer are supposed to be supported by HDL Coder.
"Compilation errors when generating code for: HDL1DDs Error during MATLAB code compilation: Error Path: /usr/local/MATLAB/R2022b/toolbox/shared/system/coder/+matlab/+system/+hdlcoder/System.p Error Location: (@Row: –> 1 @Column: –> 1) System object ‘hdl.deserializer1D’ is not supported for HDL code generation."

Can you help me find out what the problem is here? Thanks in advance. Hi, I am building a system to be deployed on an RFSoC. I have used serialize blocks on the processor to stream data through the memory using an Software to AXI4-Stream block to the Programmable Logic (PL).

Instead of using the serializer/deserializer block directly, I had to go to its library and copy its system to create a subsytem in my design containing it. That was needed because I had to access the rate transition blocks and change the parameter from "Multiple of input port sample time" to "inherit" – I did that because the system wouldn’t compile with the original parameter, throwing me the following error:
"Asynchronous sample time is found at input port 0 of Rate Transition block ‘path/to/subsystem/Serializer/rateTrans’. When Rate Transition block parameter ‘Output port sample time option’ is ‘Multiple of input port sample time’, asynchronous sample time is not allowed. Consider changing ‘Output port sample time option’ to "Specify" or "Inherit"."
I could overcome this error by changing the rate transition parameter and the model worked as expected during simulation.
When the data arrives to the PL, I need to deserialize it, which worked on simulation. However, during the build phase, I got the following error, which is rather unclear how to solve, once that the serializer/deserializer are supposed to be supported by HDL Coder.
"Compilation errors when generating code for: HDL1DDs Error during MATLAB code compilation: Error Path: /usr/local/MATLAB/R2022b/toolbox/shared/system/coder/+matlab/+system/+hdlcoder/System.p Error Location: (@Row: –> 1 @Column: –> 1) System object ‘hdl.deserializer1D’ is not supported for HDL code generation."

Can you help me find out what the problem is here? Thanks in advance. soc blockset, hdl coder, soc builder, deserializer, hardware MATLAB Answers — New Questions

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